Two-step data-line precharge scheme

1. A system comprising:

a memory device comprising:

first and second bit lines;

a first transistor configured to selectively apply a voltage reference to the first bit line in response to a control signal;

a second transistor configured to selectively apply the voltage reference to the second bit line in response to the control signal; and

a control circuit configured to supply the control signal to the first and second transistors, the control circuit comprising:

a third transistor configured to selectively apply a first voltage to gates of the first and second transistors as the control signal in response to a first command signal at a first time; and

a fourth transistor configured to selectively apply a second voltage higher than the first voltage to the gates of the first and second transistors as the control signal in response to a second command signal at a second time following the first time to reduce a precharge time of the first and second bit lines,

wherein the second voltage is greater than gate oxide withstand voltages of the first and second transistors.

2. The system of claim 1 , wherein the gate of the first transistor is coupled to the gate of the second transistor.

3. The system of claim 1 , wherein the first and second transistors are configured to charge or discharge the first and second bit lines to the voltage reference.

4. The system of claim 1 , wherein the first and second transistors are of a first conductivity type and the fourth transistor is of a second conductivity type.

5. The system of claim 1 , wherein the control circuit comprises:

a fifth transistor configured to selectively apply a third voltage to the gates of the first and second transistors as the control signal in response to the second command signal.

6. The system of claim 5 , wherein a gate of the fourth transistor is coupled to a gate of the fifth transistor, and

wherein the fifth transistor is of a first conductivity type and the fourth transistor is of a second conductivity type.

7. The system of claim 5 , wherein the memory device comprises:

a sixth transistor configured to selectively couple the first bit line to the second bit line in response to the control signal,

wherein a gate of the sixth transistor is coupled to the gates of the first and second transistors.

8. The system of claim 7 , wherein the first, second, fifth, and sixth transistors are of a first conductivity type and the fourth transistor is of a second conductivity type different than the first conductivity type.

9. The system of claim 7 , wherein the control circuit is configured to apply the first voltage to the gates of the first, second, and sixth transistors to turn on one or more of the first, second, and sixth transistors, and to apply the second voltage to the gates of the first, second, and sixth transistors to strengthen a current drive capability of the one or more of the first, second, and sixth transistors.

10. The system of claim 1 , wherein the control circuit is configured to:

control the third transistor to apply the first voltage to the gates of the first and second transistors for a first portion of a precharge period; and

control the fourth transistor to apply the second voltage to the gates of the first and second transistors for a second portion of the precharge period to strengthen a current drive capability of the first and second transistors.

11. The system of claim 1 , wherein the control circuit is configured to:

apply the first voltage to the gates of the first and second transistors at the first time using the third transistor to turn on one or both of the first and second transistors; and

transition the gates of the first and second transistors from the first voltage to the second voltage at the second time using the fourth transistor to strengthen a current drive capability of one or both of the first and second transistors,

wherein, at the second time, voltages of the first and second bit lines are greater than ground and approaching the voltage reference.

12. The system of claim 1 , wherein the first and second transistors comprise first and second gate oxides having a first and second thicknesses, and

wherein the third and fourth transistors comprise third and fourth gate oxides having third and fourth thicknesses, the third and fourth thicknesses thicker than the first and second thicknesses.

13. A system comprising:

a memory device comprising:

a first bit line; and

a first transistor configured to selectively apply a voltage reference to the first bit line in response to a control signal; and

a control circuit configured to apply, as the control signal, a first voltage to a gate of the first transistor in response to a first command signal at a first time, and a second voltage higher than the first voltage to the gate of the first transistor in response to a second command signal at a second time following the first time to reduce a precharge time of the first bit line,

wherein the second voltage is greater than a gate oxide withstand voltage of the first transistor.

14. The system of claim 13 , wherein the control circuit is configured to:

apply the first voltage to the gate of the first transistor for a first portion of a precharge period; and

apply the second voltage to the gate of the first transistor for a second portion of the precharge period to strengthen a current drive capability of the first transistor.

15. The system of claim 14 , wherein, at the second time, a voltage of the first bit line is greater than ground and approaching the voltage reference.

16. A method comprising:

selectively applying a voltage reference to a first bit line of a memory device using a first transistor in response to a control signal;

applying, using a control circuit, a first voltage to a gate of the first transistor in response to a first command signal at a first time, and a second voltage higher than the first voltage to the gate of the first transistor in response to a second command signal at a second time following the first time to reduce a precharge time of the first bit line,

wherein the second voltage is greater than gate oxide withstand voltages of the first and second transistors.

17. The method of claim 16 , comprising:

selectively applying the voltage reference to a second bit line of the memory device using a second transistor in response to the control signal;

applying, using the control circuit, the first voltage to a gate of the second transistor in response to the first command signal at the first time, and the second voltage higher than the first voltage to the gate of the second transistor in response to the second command signal at the second time following the first time to reduce a precharge time of the second bit line,

wherein applying the first voltage to the gates of the first and second transistors includes using a third transistor, and

wherein applying the second voltage to the gates of the first and second transistors includes using a fourth transistor.

18. The method of claim 17 , wherein applying the first voltage to the gates of the first and second transistors comprises applying the first voltage for a first portion of a precharge period, and

wherein applying the second voltage to the gates of the first and second transistors comprises applying the second voltage for a second portion of the precharge period to strengthen a current drive capability of the first and second transistors.

19. The method of claim 17 , wherein, at the second time, voltages of the first and second bit line are greater than ground and approaching the voltage reference.

20. A system comprising:

a memory device comprising:

first and second bit lines;

a first transistor configured to selectively apply a voltage reference to the first bit line in response to a control signal;

a second transistor configured to selectively apply the voltage reference to the second bit line in response to the control signal; and

a control circuit configured to supply the control signal to the first and second transistors, the control circuit comprising:

a third transistor configured to selectively apply a first voltage to gates of the first and second transistors as the control signal in response to a first command signal at a first time;

a fourth transistor configured to selectively apply a second voltage higher than the first voltage to the gates of the first and second transistors as the control signal in response to a second command signal at a second time following the first time to reduce a precharge time of the first and second bit lines; and

a fifth transistor configured to selectively apply a third voltage to the gates of the first and second transistors as the control signal in response to the second command signal,

wherein a gate of the fourth transistor is coupled to a gate of the fifth transistor, and

wherein the fifth transistor is of a first conductivity type and the fourth transistor is of a second conductivity type.

21. The system of claim 20 , wherein the second voltage is greater than gate oxide withstand voltages of the first and second transistors.

22. The system of claim 20 , wherein the first and second transistors comprise first and second gate oxides having a first and second thicknesses, and

wherein the third and fourth transistors comprise third and fourth gate oxides having third and fourth thicknesses, the third and fourth thicknesses thicker than the first and second thicknesses.

23. A system comprising:

a memory device comprising:

first and second bit lines;

a first transistor configured to selectively apply a voltage reference to the first bit line in response to a control signal;

a second transistor configured to selectively apply the voltage reference to the second bit line in response to the control signal; and

a control circuit configured to supply the control signal to the first and second transistors, the control circuit comprising:

a third transistor configured to selectively apply a first voltage to gates of the first and second transistors as the control signal in response to a first command signal at a first time; and

a fourth transistor configured to selectively apply a second voltage higher than the first voltage to the gates of the first and second transistors as the control signal in response to a second command signal at a second time following the first time to reduce a precharge time of the first and second bit lines;

wherein the first and second transistors comprise first and second gate oxides having a first and second thicknesses, and

wherein the third and fourth transistors comprise third and fourth gate oxides having third and fourth thicknesses, the third and fourth thicknesses thicker than the first and second thicknesses.

24. The system of claim 23 , wherein the control circuit comprises:

a fifth transistor configured to selectively apply a third voltage to the gates of the first and second transistors as the control signal in response to the second command signal,

wherein a gate of the fourth transistor is coupled to a gate of the fifth transistor, and

wherein the fifth transistor is of a first conductivity type and the fourth transistor is of a second conductivity type.

25. The system of claim 23 , wherein the second voltage is greater than gate oxide withstand voltages of the first and second transistors.