Reduced peak self-refresh current in a memory device
Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.
1. A memory device, comprising:
a memory controller comprising a self-refresh clock; and
a plurality of memory units, wherein each memory unit in a first subset of the plurality of memory units is configured to self-refresh during a first self-refresh cycle indicated by a first pulse of the self-refresh clock, and each memory unit in a second subset of the plurality of memory units is configured to self-refresh during a second self-refresh cycle indicated by a second pulse of the self-refresh clock, wherein a first memory unit in the first subset is configured to count pulses of the self-refresh clock and to self-refresh itself in response to a first number of counted pulses of the self-refresh clock, and a second memory unit in the second subset is configured to count pulses of the self-refresh clock and to self-refresh itself in response to a second number of counted pulses of the self-refresh clock.
2. The memory device of claim 1 , wherein each memory unit in a third subset of the plurality of memory units is configured to self-refresh during a third self-refresh cycle indicated by a third pulse of the self-refresh clock, and each memory unit in a fourth subset of the plurality of memory units is configured to self-refresh during a fourth self-refresh cycle indicated by a fourth pulse of the self-refresh clock.
3. The memory device of claim 2 , wherein:
each memory unit in a fifth subset of the plurality of memory units is configured to self-refresh during a fifth self-refresh cycle indicated by a fifth pulse of the self-refresh clock;
each memory unit in a sixth subset of the plurality of memory units is configured to self-refresh during a sixth self-refresh cycle indicated by a sixth pulse of the self-refresh clock;
each memory unit in a seventh subset of the plurality of memory units is configured to self-refresh during a seventh self-refresh cycle indicated by a seventh pulse of the self-refresh clock; and
each memory unit in an eighth subset of the plurality of memory units is configured to self-refresh during an eighth self-refresh cycle indicated by an eighth pulse of the self-refresh clock.
4. The memory device of claim 1 , wherein a frequency of the self-refresh clock is N times a frequency that has a wavelength shorter than a maximum refresh duration for any individual memory unit of the plurality of memory units where N is a number of different subsets with different self-refresh cycles in the plurality of memory units.
5. The memory device of claim 1 , wherein each memory unit comprises one or more memory banks each comprising a plurality of capacitors, wherein the self-refresh clock is configured to cause the capacitors of the plurality of capacitors to self-refresh before stored charges in the capacitors is lost due to charge leakage of the capacitors.
6. The memory device of claim 5 , wherein the self-refresh comprises:
reading data from the plurality of capacitors; and
writing back the data to the plurality of capacitors.
7. The memory device of claim 6 , wherein the self-refresh is completed without direction from a host device coupled to the memory device.
8. The memory device of claim 5 , wherein each memory unit comprises a die each comprising a plurality of memory banks.
9. The memory device of claim 1 , wherein self-refreshes of each memory unit in the first subset of the plurality of memory units occur simultaneously.
10. The memory device of claim 1 , wherein self-refreshes of each memory unit in the first subset of the plurality of memory units occur within 4-8 ns of each other.
11. The memory device of claim 1 , comprising a memory die comprising the plurality of memory units, wherein the plurality of memory units comprises a plurality of memory banks in a memory die.
12. The memory device of claim 1 , wherein the plurality of memory units comprises a plurality of memory dies in a stack each including a plurality of memory banks.
13. A method comprising:
organizing memory units of a memory device into a number of groups; and
self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock, wherein separately refreshing each group comprises at least one memory unit in each memory group configured to count pulses of the self-refresh clock and to self-refresh itself in response to a counted number of pulses of the self-refresh clock.
14. The method of claim 13 , wherein a frequency of the self-refresh clock is equal to a refresh rate of any memory unit of the memory units times the number.
15. The method of claim 13 , wherein self-refreshing a group of memory units comprises self-refreshing each memory unit of a respective memory unit simultaneously.
16. The method of claim 13 , wherein self-refreshing a group of memory units comprises self-refreshing each memory unit of a respective memory unit with a 4-8 ns stagger between each self-refresh.
17. The method of claim 13 , wherein the at least one memory unit is a master for a respective memory unit group and is configured to send an indication to other memory units in the respective memory unit group to cause the other memory units to self-refresh.
18. A memory device, comprising:
a memory controller configured to output a self-refresh clock; and
a plurality of memory units configured to:
receive the self-refresh clock; and
sequentially refresh groups of the plurality of memory units using sequential pulses of the self-refresh clock, wherein each pulse of the self-refresh clock induces a self-refresh cycle that causes refresh in a single group of the refresh groups, wherein a first memory unit corresponding to a first refresh group is configured to:
count pulses of the self-refresh clock; and
after a number corresponding to the first refresh group has been counted, refresh the first memory unit.
19. The memory device of claim 18 , wherein sequentially and separately refreshing groups of the plurality of memory units comprises refreshing memory units of a respective group by staggering refreshing of the memory units of the respective group within a single refresh cycle.
20. The memory device of claim 18 , wherein the first memory unit is configured to send an indication of the count to a second memory unit corresponding to the first refresh group, and the second memory unit is configured to:
receive the indication of the count from the first memory unit; and
in response to receiving the indication, refresh the second memory unit.