IP Library Granted Patent US 11,211,131
Granted Patent B2
US 11,211,131 · App. 16/214,373 · Granted Dec 28, 2021

Adjusting program effective time using program step characteristics

Inventor: Bruce A. Liikanen (Berthoud, CO)
Assignee: Micron Technology, Inc.
G11C16/32G06F3/0604G06F3/0629G06F3/0679G11C16/10G11C16/349G11C16/0483
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Quick Facts
Patent No.
US 11,211,131
App. No.
16/214,373
Granted
Dec 28, 2021
Kind
B2
Abstract

A program effective time (PET) for programming at least a portion of a plurality of memory cells based on one or more program step characteristics is determined. The determined PET and a target PET is compared. In response to the determined PET being different than the target PET, the one or more program step characteristics is adjusted to adjust the determined PET to the target PET.

Claims (44)

1. A system, comprising:

a memory component including a plurality of memory cells; and

a processing device coupled to the memory component and configured to:

determine a program effective time (PET) for programming at least a portion of the plurality of memory cells based on one or more program step characteristics, wherein the one or more program step characteristics comprises one or more of a program step size and a program step duration;

compare the determined PET to a target PET;

determine a particular proportion of adjustment of the program step size and the program step duration to adjust the determined PET toward the target PET; and

in response to the determined PET being different than the target PET and independent of the one or more program step characteristics reaching a threshold, adjust the program step size and the program step duration to adjust the determined PET to the target PET, wherein adjustment of the program step size is in the particular proportion to the adjustment of the program step duration based on a determined relationship between the program step size and the program step duration.

2. The system of claim 1 , wherein the processing device is further configured to adjust the program step size without adjusting a program step duration to adjust the determined PET to the target PET.

3. The system of claim 1 , wherein the processing device is further configured to adjust the program step duration without adjusting a program step size to adjust the determined PET to the target PET.

4. The system of claim 1 , wherein the processing device configured to adjust the one or more program step characteristics comprises the processing device configured to:

adjust the program step size a particular amount to adjust the determined PET a first particular degree;

adjust the program step duration a particular amount to adjust the determined PET a second particular degree; and

in response to adjusting the determined PET the first particular degree and the second particular degree, adjusting the determined PET to the target PET.

5. The system of claim 1 , wherein the processing device is further configured to adjust the one or more program step characteristics based on implementing a target calibration mechanism to calibrate a target profile during operation of the memory component.

6. The system of claim 1 , wherein the processing device is further configured to balance a programming time and an error measure associated with writing the data in the memory component based on the one or more program step characteristics that is adjusted.

7. The system of claim 1 , wherein the processing device is further configured to determine that the determined PET has changed from being at the target PET to a non-target PET.

8. The system of claim 7 , wherein the processing device is further configured to, in response to determining that the determined PET is at the non-target PET, adjust one or more program step characteristics to adjust the non-target PET to the target PET.

9. The system of claim 1 , wherein:

the processing device is further configured to:

determine a step threshold for adjusting a program step size; and

determine a time threshold for adjusting a program step duration.

10. A method, wherein the method comprises:

determining a program effective time (PET) for programming at least a portion of a plurality of memory cells of a memory component based on one or more program step characteristics, wherein the one or more program step characteristics comprises one or more of a program step size and a program step duration;

comparing the determined PET to a target PET;

determining a particular proportion of adjustment of the program step size and the program step duration to adjust the determined PET toward the target PET; and

in response to the determined PET being different than the target PET and independent of whether the one or more program step characteristics reaches a threshold, adjusting the program step size and the program step duration to adjust the determined PET to an adjusted PET, wherein adjustment of the program step size is in the particular proportion to the adjustment of the program step duration based on a determined relationship between the program step size and the program step duration;

comparing the adjusted PET to the target PET; and

in response to the adjusted PET being different than the target PET, further adjusting one or more of the program step characteristics to adjust the adjusted PET to the target PET.

11. The method of claim 10 , further comprising repeating a comparison of a previously adjusted PET to the target PET.

12. The method of claim 11 , wherein, in response to the previously adjusted PET being a different PET than the target PET, adjusting one or more of the program step characteristics until the previously adjusted PET is a same PET as the target PET.

13. The method of claim 10 , wherein the memory component comprises a plurality of memory dies, and wherein the method further comprises:

programming each of the plurality of memory dies using the adjusted PET that is a same PET as the target PET.

14. A system, comprising:

a memory component including a plurality of memory cells; and

a processing device coupled to the memory component and configured to:

determine a particular proportion of concurrent adjustment of the program step size and the program step duration to adjust the determined PET toward the target PET; and

adjust one or more program step characteristics by determined amounts to adjust a program effective time (PET) for programming at least a portion of the plurality of memory cells, wherein:

the one or more program step characteristics comprise one or more of a program step size and a program step duration;

the program step size and the program step duration are adjusted based on a determined relationship between a program step size and a program step duration, wherein the program step size is adjusted the particular proportion with respect to the adjustment of the program step duration based on the determined relationship; and

the program step size and the program step duration are adjusted independent of the one or more program step characteristics having reached a threshold.

15. The system of claim 14 , wherein the processing device is further configured to repeatedly adjust the one or more program step characteristics to maintain a constant PET at a target PET.

16. The system of claim 14 , wherein the processing device is further configured to adjust the one or more program step characteristics in response to a change in programming of the memory component.

17. The system of claim 16 , wherein the change in programming comprises a change due to wear cycling of the memory component.

18. The system of claim 16 , wherein the change in programming comprises a temperature change in the memory component.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2018
From: LIIKANEN, BRUCE A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047723/0711 →
Continuity (1)
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