Stacked semiconductor die assemblies with die substrate extensions
View Patent ↗Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a mold material around a portion of a parameter of a semiconductor substrate, wherein the mold material extends outwardly from the portion of the semiconductor substrate and defines a planform of a first die;
attaching a second die to the first die to form a die stack, wherein attaching the second die includes attaching the second die to the semiconductor substrate and the mold material; and
mounting the die stack to a package substrate, wherein the second die is between the package substrate and the first die, and wherein the mold material of the first die extends beyond the second die and overhangs the package substrate.
2. The method of claim 1 wherein the mounting includes attaching the package substrate to both the semiconductor substrate and the mold material of the first die.
3. The method of claim 1 wherein the mounting includes attaching the second die to the package substrate.
4. The method of claim 3 wherein the mold material is a first mold material, and wherein the method further comprises molding a second mold material over the first mold material to form a package casing.
5. The method of claim 1 wherein the molding includes:
attaching the semiconductor substrate of the first die to a temporary carrier;
molding the mold material over the semiconductor substrate and the temporary carrier; and
thinning the mold material to expose a first surface of the semiconductor substrate and a second surface of the mold material, wherein the first surface is adjacent the second surface.
6. The method of claim 5 , further comprising attaching the package substrate to the first and second surfaces.
7. The method of claim 5 , further comprising attaching the second die to the first and second surfaces.
8. The method of claim 5 , further comprising flowing an encapsulant over the package substrate and the die stack after the molding.
9. The method of claim 1 wherein at least one of the first and second dies is a memory die.
10. The method of claim 9 wherein the semiconductor substrate of the first die includes a controller circuit.
11. The method of claim 1 wherein the first die defines a first perimeter, and wherein the second die defines a second perimeter, and wherein the first and second perimeters overlap each other.
12. The method of claim 11 wherein the first die has a first outer edge, and wherein the first and second perimeters overlap each other such that a region of the first outer edge overhangs a portion of the package substrate.
13. The method of claim 12 wherein the region of the first outer edge overhangs the portion of the package substrate by a first distance.
14. The method of claim 13 wherein the second die has a second outer edge, and wherein the first and second perimeters overlap each other such that a region of the second outer edge extends a second distance beyond the first outer edge.