Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to:

determine a plurality of difference error counts (Diff-EC) that are indicative of relative widths of valleys, wherein each of the valleys is located between a respective pair of program distributions of a memory cell of the memory device; and

perform a program targeting operation on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions, wherein to perform the program targeting operation, the processing device is to:

select a rule from a set of rules based on the plurality of difference error counts, wherein the set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution; and

adjust, based on the selected rule, the one or more program verify (PV) targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

2. The system of claim 1 , wherein the initial programming distribution corresponds to one of the programming distributions of the memory cell having a lowest PV target.

3. The system of claim 1 , wherein the set of rules further corresponds to an adjusting of a PV target of a programming distribution corresponding to a highest PV target.

4. The system of claim 1 , wherein the set of rules further corresponds to a locking of a PV target of a programming distribution corresponding to a highest PV target.

5. The system of claim 1 , wherein the program targeting operation implements the set of rules to balance logical page types such that a bit error rate (BER) is approximately a same BER for different logical page types, and to equalize relative widths of valleys of a particular logical page type such that read window budgets (RWB) for the valleys of the particular logical page type are approximately a same RWB.

6. The system of claim 1 , wherein to select the rule from the set of rules based on the plurality of difference error counts, the processing device is further to:

identify a first logical page type and a second logical page type; and

determine whether a bit error rate (BER) for the first logical page type is less than or greater than a BER for the second logical page type; and

responsive to determining that the BER for the first logical page type is less than the BER for the second logical page type, identify a first subset of the set of rules, wherein the selected rule is from the first subset of rules.

7. The system of claim 6 , wherein to select the rule from the set of rules based on the plurality of difference error counts, the processing device is further to:

responsive to determining that the BER for the first logical page type is greater than the BER for the second logical page type, identify a second subset of the set of rules, wherein the selected rule is from the second subset of rules.

8. The system of claim 6 , wherein to determine whether the BER for the first logical page type is less than or greater than the BER for the second logical page type, the processing device is further to:

compare a first average center bit error count associated with the first logical page type to a second average center bit error count associated with the second logical page type, wherein the BER for the first logical page type is less than the BER for the second logical page type when the first average center bit error count is less than the second average center bit error count, and wherein the BER for the first logical page type is greater than the BER for the second logical page type when the first average center bit error count is greater than the second average center bit error count.

9. The system of claim 6 , the processing device is further to:

identify a rule from the first subset of rules based on a valley that has a largest relative width for the first logical page type and a valley that has a least relative width for the second logical page type.

10. The system of claim 9 , wherein the plurality of difference error counts are used to determine the valley that has the largest relative width for the first logical page type and the valley that has the least relative width for the second logical page type.

11. The system of claim 1 , wherein to select the rule from the set of rules based on the plurality of difference error counts, the processing device is further to:

select the rule from the set of rules that identifies at least two of the plurality of program verify (PV) targets describing an adjusting such that a relative width of a valley that has a lowest Diff-EC for a first logical page type is decreased and a relative width of a valley that has a highest Diff-EC for a second logical page type is increased.

12. The system of claim 1 , wherein to adjust, based on the selected rule, the one or more program verify (PV) targets of the plurality of PV targets associated with the programming distributions the processing device is further to adjust at least the PV target of the programming distribution adjacent to the initial programming distribution.

13. The system of claim 1 , wherein the processing device is further to perform the program targeting operation responsive to a satisfaction of one or more conditions.

14. A method comprising:

determining, by a processing device, a plurality of difference error counts (Diff-EC) that are indicative of relative widths of valleys, wherein each of the valleys is located between a respective pair of programming distributions of a memory cell of a memory device; and

performing a program targeting operation on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions, wherein performing the program targeting operation comprises:

selecting a rule from a set of rules based on the plurality of difference error counts, wherein the set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution; and

adjusting, based on the selected rule, the one or more program verify (PV) targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

15. The method of claim 14 , wherein the initial programming distribution corresponds to one of the programming distributions of the memory cell having a lowest PV target.

16. The method of claim 14 , wherein the set of rules further corresponds to an adjusting of a PV target of a programming distribution corresponding to a highest PV target.

17. A non-transitory computer-readable medium comprising instruction that, responsive to execution by a processing device, cause the processing device to perform operations comprising:

determining, by the processing device, a plurality of difference error counts (Diff-EC) that are indicative of relative widths of valleys, wherein each of the valleys is located between a respective pair of programming distributions of a memory cell of a memory device; and

performing a program targeting operation on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions, wherein performing the program targeting operation comprises:

selecting a rule from a set of rules based on the plurality of difference error counts, wherein the set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution; and

adjusting, based on the selected rule, the one or more program verify (PV) targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

18. The non-transitory computer-readable medium of claim 17 , wherein the initial programming distribution corresponds to one of the programming distributions of the memory cell having a lowest PV target.

19. The non-transitory computer-readable medium of claim 17 , wherein the set of rules further corresponds to an adjusting of a PV target of a programming distribution corresponding to a highest PV target.

20. The non-transitory computer-readable medium of claim 17 , wherein the program targeting operation implements the set of rules to balance logical page types such that a bit error rate (BER) is approximately a same BER for different logical page types, and to equalize relative widths of valleys of a particular logical page type such that read window budgets (RWB) for the valleys of the particular logical page type are approximately a same RWB.