3D stacked integrated circuits having failure management
View Patent ↗A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
1. A three-dimensional stacked integrated circuit (3D SIC), comprising:
a non-volatile memory die;
a volatile memory die; and
a logic die,
wherein the non-volatile memory die, the volatile memory die, and the logic die are stacked and the logic die is in between the non-volatile memory die and the volatile memory die,
wherein the 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies,
wherein each column of the plurality of columns is configurable to be bypassed via configurable routes, and
wherein the configurable routes are configured to re-route functionality of the column to a corresponding part of a neighboring column based at least in part on a quantity of bit errors in the column exceeding a threshold.
2. The 3D SIC of claim 1 , wherein the neighboring column is positioned next to the column without an intermediate column between the neighboring column and the column.
3. The 3D SIC of claim 2 , wherein the neighboring column is a spare column configured to receive re-routed functionality from one or more other columns including the column.
4. The 3D SIC of claim 3 , wherein logic circuitry in the 3D SIC is configured to reserve the neighboring column as the spare column when an error detecting logic circuit determines that a quantity of bit errors in the column exceeds a threshold.
5. The 3D SIC of claim 1 , wherein the configurable routes are configured to re-route the functionality of the column to the neighboring column in response to an error detecting logic circuit in the 3D SIC determining that a quantity of bit errors in the column exceeds a threshold.
6. The 3D SIC of claim 1 , wherein the configurable routes are configured to re-route the functionality of the column to the neighboring column when a communication does not travel through a signal route of the column.
7. The 3D SIC of claim 6 , wherein each column comprises a thorough silicon via (TSV) that connects the non-volatile memory die, the volatile memory die, and the logic die, and wherein the configurable routes are configured to re-route the functionality of the column to the neighboring column when a communication does not travel through the TSV of the column.
8. The 3D SIC of claim 7 , wherein the configurable routes are configured to re-route a communication to a TSV of the neighboring column, when the communication does not travel through the TSV of the column.
9. The 3D SIC of claim 6 , wherein each column comprises a 3D XPoint (3DXP) partition of the non-volatile memory die and the 3DXP partition comprises a plurality of non-volatile memory cells, wherein each cell comprises two intersecting interconnects, and wherein the configurable routes are configured to re-route a communication initially directed to an interconnect of two interconnects of a cell of the column to a corresponding cell of the neighboring column, when the communication does not travel through the interconnect the cell of the column.
10. The 3D SIC of claim 6 , wherein the non-volatile memory die comprises a plurality of 3D XPoint (3DXP) partitions and a plurality of interconnects connecting each 3DXP partition to its neighboring partitions, and wherein the configurable routes are configured to re-route a communication initially directed to an interconnect of the plurality of interconnects to a corresponding 3DXP partition of a neighboring column, when the communication does not travel through the interconnect.
11. The 3D SIC of claim 1 , wherein the configurable routes are configured to re-route the functionality of the column to the neighboring column in response to an error detecting logic circuit in the 3D SIC determining a retrieved result is unexpected at the column.
12. The 3D SIC of claim 11 , wherein each column comprises a 3D XPoint (3DXP) partition of the non-volatile memory die and the 3DXP partition comprises a plurality of non-volatile memory cells, wherein each cell comprises a retrievable result, and wherein the configurable routes are configured to re-route storage of data directed to a non-volatile memory cell of the column to a corresponding non-volatile memory cell of the neighboring column, in response to the error detecting logic circuit determining a retrieved result is unexpected at the column.
13. The 3D SIC of claim 1 , wherein the configurable routes are configured to re-route the functionality of the column to the neighboring column in response to an error detecting logic circuit in the 3D SIC determining a retrieved calculated result is unexpected at the column.
14. The 3D SIC of claim 13 , wherein each column comprises a logic partition of the logic die, wherein each logic partition comprises a retrievable calculated result, and wherein the configurable routes are configured to re-route a data processing request directed to a logic partition of the column to a corresponding logic partition of the neighboring column, in response to the error detecting logic circuit determining a retrieved calculated result is unexpected at the column.
15. A three-dimensional stacked integrated circuit (3D SIC), comprising:
a 3D XPoint (3DXP) memory die;
a dynamic random-access memory (DRAM) die; and
a logic die,
wherein the 3DXP memory die, the DRAM die, and the logic die are stacked and the logic die is in between the 3DXP memory die and the DRAM die,
wherein the 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies,
wherein each column of the plurality of columns is configurable to be bypassed via configurable routes, and
wherein the configurable routes are configured to re-route functionality of a part of the column to a corresponding part of a neighboring column.
16. The 3D SIC of claim 15 , wherein the configurable routes are configured to re-route the functionality of the part of the column to the corresponding part of the neighboring column in response to an error detecting logic circuit in the 3D SIC determining that the part of the column is failing.
17. The 3D SIC of claim 16 , wherein the error detecting logic circuit is configured to determine that the part of the column is failing when a communication does not travel through a signal route of the part of the column.
18. The 3D SIC of claim 16 , wherein the error detecting logic circuit is configured to determine that the part of the column is failing when a retrieved result is unexpected at the part of the column.
19. The 3D SIC of claim 16 , wherein the error detecting logic circuit is configured to determine that the part of the column is failing based at least in part on a quantity of bit errors in the column exceeding a threshold.
20. A three-dimensional stacked integrated circuit (3D SIC), comprising:
a 3D XPoint (3DXP) memory die;
a memory die; and
a logic die,
wherein the 3DXP memory die, the memory die, and the logic die are stacked and the logic die is in between the 3DXP memory die and the memory die,
wherein the 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies,
wherein each column of the plurality of columns is configurable to be bypassed via configurable routes,
wherein the configurable routes are configured to re-route functionality of a failing part of the column to a corresponding effective part of a spare neighboring column, and
wherein the spare column is reserved to receive re-routed functionality from one or more other columns.