Offset cancellation of duty cycle detector

1. An apparatus, comprising:

a duty cycle adjustment circuit configured to receive an input clock signal and output a system clock signal that is transmitted to a clock distribution network, the duty cycle adjustment circuit further configured to adjust a duty cycle of the input clock signal based on an average code value that mitigates distortions in the system clock signal;

a duty cycle detector circuit having a first detector input to receive a first clock signal from the clock distribution network and a second detector input to receive a second clock signal from the clock distribution network, the duty cycle detector configured to output a duty cycle status signal that indicates whether the first clock signal is above a 50% duty cycle or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal; and

a counter logic circuit configured to determine the average code value based on the duty cycle status signal, the counter logic circuit automatically canceling an offset of the duty cycle detector when determining the average code value,

wherein the average code value is an average of an initial code value based on the comparison of the first clock signal to the second clock signal and a flipped code value based on a comparison of a third signal that is complementary to the first clock signal and a fourth signal that is complementary to the second clock signal.

2. The apparatus of claim 1 , wherein the average code value corresponds to a bit code, and

wherein the duty cycle adjustment circuit selectively operates pull-up circuits, pull-down circuits or both pull-up circuit and pull-down circuits based on a value of the bit code.

3. The apparatus of claim 1 , wherein the average code value is used by the duty cycle adjustment circuit during in-service operations.

4. An apparatus, comprising:

a duty cycle adjustment circuit configured to receive an input clock signal and output a system clock signal that is transmitted to a clock distribution network, the duty cycle adjustment circuit further configured to adjust a duty cycle of the input clock signal based on an average code value that mitigates distortions in the system clock signal;

a duty cycle detector circuit having a first detector input to receive a first clock signal from the clock distribution network and a second detector input to receive a second clock signal from the clock distribution network, the duty cycle detector configured to output a duty cycle status signal that indicates whether the first clock signal is above a 50% duty cycle or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal; and

a counter logic circuit configured to determine the average code value based on the duty cycle status signal, the counter logic circuit automatically canceling an offset of the duty cycle detector when determining the average code value,

wherein the automatic cancellation of the offset when determining the average code value comprises:

determining an initial code value based on the duty cycle status signal when the duty cycle correction circuit is in an initial mode of operation, the initial code value corresponding to first distortions in the first clock signal based on a comparison to the second clock signal;

determining a flipped code value based on the duty cycle status signal when the duty cycle correction circuit is in a flipped mode of operation, the flipped code value corresponding to second distortions in the first clock signal based on a comparison to the second signal; and

averaging the initial code value and the flipped code value so as to cancel the offset of the duty cycle detector and determine the average code value,

wherein, in the initial mode of operation, the first clock signal corresponds to the system clock signal and the second clock signal corresponds to a signal complimentary to the system clock signal, and

wherein, in the flipped mode of operation, the first clock signal corresponds to the signal complimentary to the system clock signal and the second clock signal corresponds to the system clock signal.

5. The apparatus of claim 4 , further comprising:

a switching circuit configured to direct the system clock signal to the first detector input and the complementary system clock signal to the second detector input when the duty cycle correction circuit is in the initial mode of operation and configured to direct the complementary system clock signal to the first detector input and the system clock signal to the second detector input when the duty cycle correction circuit is in the flipped mode of operation.

6. The apparatus of claim 4 , wherein the determining of the initial code value includes locking in the initial code value after the duty cycle status signal reaches a dither condition, and

wherein the determining of the flipped code value includes locking in the final code value after the duty cycle status signal reaches the dither condition.

7. The apparatus of claim 4 , wherein the initial code value further corresponds to the offset of the duty cycle detector and the flipped code value further corresponds to the offset of the duty cycle detector.

8. The apparatus of claim 4 , wherein the average code value corresponds to a bit code, and

wherein the duty cycle adjustment circuit selectively operates pull-up circuits, pull-down circuits or both pull-up circuit and pull-down circuits based on a value of the bit code.

9. The apparatus of claim 4 , wherein the average code value is used by the duty cycle adjustment circuit during in-service operations.