Power noise reduction technique for high density memory with frequency adjustments

1. A memory device comprising:

a charge pump comprising:

an oscillator; and

a set of charge pump cores, each charge pump core configured to receive an oscillator signal from the oscillator, and a first voltage, and to generate a second voltage higher than the first voltage; and

a memory controller configured to:

receive an instruction associated with a memory operation; and

generate a first control signal to the oscillator of the charge pump based on the instruction, wherein the first control signal is configured to adjust a frequency of the oscillator signal.

2. The memory device of claim 1 , wherein the charge pump comprises a set of delay elements arranged in a chain, wherein the set of delay elements is configured to receive the oscillator signal and to provide a set of delayed oscillator signals, wherein each charge pump core of the set of charge pump cores is configured to receive a respective delayed oscillator signal, and wherein the memory controller is configured to generate a second control signal configured to adjust a delay of at least one delay element of the set of delay elements.

3. The memory device of claim 2 , wherein the set of charge pump cores has a number N of charge pump cores, the oscillator signal has a frequency f, and the second control signal is configured to adjust the delay of the at least one delay element to a period equal to (f×N) −1 .

4. The memory device of claim 1 , wherein the first voltage comprises an activating power supply (V PP ), or a power supply (V DD ).

5. The memory device of claim 1 , wherein the memory operation comprises an operation that has a high charge demand, and wherein the first control signal comprises a frequency increase request.

6. The memory device of claim 1 , wherein the memory operation comprises an operation that has a low charge demand, and wherein the control signal comprises a frequency decrease request.

7. The memory device of claim 1 , wherein the memory operation comprises a read operation, a write operation, or a refresh operation.

8. A memory device comprising:

a plurality of memory cells;

a controller configured to receive a first memory operation of a plurality of memory operations;

first circuitry configured to perform the first memory operation;

a charge pump comprising:

an oscillator configured to receive a first control signal from the controller configured to change a frequency of an oscillator signal provided by the oscillator; and

a plurality of charge pump cores, wherein each charge pump core is configured to receive the oscillator signal and a first voltage, and to generate a second voltage higher than the first voltage, wherein the second voltage is configured to power the first circuitry during performance of the first memory operation, and wherein a charge associated with the second voltage is based on the frequency of the oscillator signal.

9. The memory device of claim 8 , comprising a memory die that comprises the plurality of memory cells, wherein the memory die comprises 8 Gb, 16 Gb, or 32 Gb.

10. The memory device of claim 8 , wherein the charge pump comprises a plurality of delay elements arranged in a chain that receives the oscillator signal, wherein the plurality of delay elements is configured to generate a plurality of delayed oscillator signals and each charge pump core is configured to receive one delayed oscillator signal of the plurality of delayed oscillator signals.

11. The memory device of claim 10 , wherein the controller is configured to generate a second control signal that adjusts a delay of each delay element of the plurality of delay elements.

12. The memory device of claim 11 , wherein the plurality of charge pump cores has a number N of charge pump cores, the oscillator signal has a frequency f, and the second control signal is configured to adjust each delay element of the plurality of delay elements to cause the delay to be approximately (f×N) −1 .

13. The memory device of claim 11 , wherein the first control signal is configured to increase the frequency and the second control signal is configured to reduce the delay.

14. The memory device of claim 8 , wherein the plurality of memory operations comprises a read operation, a write operation, or a refresh operation.

15. The memory device of claim 8 , wherein the first voltage comprises an activating power supply (V PP ), or a power supply (V DD ).

16. A method for controlling charge pump circuitry of a memory device, comprising:

receiving, in a controller, a command for a memory operation of a set of operations;

determining, in the controller, a charge demand based in part on the memory operation;

determining, in the controller, an adjustment to a frequency of an oscillator of the charge pump circuitry; and

providing a first control signal from the controller to the oscillator of the charge pump circuitry to cause a change to the frequency of the oscillator.

17. The method of claim 16 , comprising providing a second control signal from the controller to a delay element of the charge pump circuitry, based on the adjustment to the frequency of the oscillator, wherein the delay element is configured to receive an oscillator signal from the oscillator and generate a delayed oscillator signal to a charge pump core of the charge pump circuitry.

18. The method of claim 17 , wherein the charge pump circuitry comprises N charge pump cores, the frequency of the oscillator has a value f, and the second control signal is configured to adjust the delay element to cause the delay approximately equal to (f×N) −1 .

19. The method of claim 16 , wherein the first control signal comprises an increase of frequency request or a decrease of frequency request.

20. The method of claim 16 , wherein the first control signal comprises a target frequency request.