IP Library Granted Patent US 10,629,547
Granted Patent B1
US 10,629,547 · App. 16/174,871 · Granted Apr 21, 2020

Redistribution-layer fanout package stiffener

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Quick Facts
Patent No.
US 10,629,547
App. No.
16/174,871
Granted
Apr 21, 2020
Kind
B1
Abstract

An apparatus may include a packaging substrate. The apparatus may further include multiple semiconductor devices attached to the packaging substrate, the multiple semiconductor devices defining a path along the packaging substrate between a pair of the multiple semiconductor devices. The apparatus may also include a stiffener structure coupled to the packaging substrate and positioned with a longitudinal axis of the stiffener structure being perpendicular to the path.

Claims (30)

1. An apparatus comprising:

a packaging substrate, wherein the packaging substrate is a redistribution layer, and wherein the redistribution layer includes a copper fanout structure positioned in a molding compound;

multiple semiconductor devices attached to the packaging substrate, the multiple semiconductor devices defining a path along the packaging substrate between a first pair of the multiple semiconductor devices; and

a stiffener structure coupled to the packaging substrate and positioned with a longitudinal axis of the stiffener structure being perpendicular to the path.

2. The apparatus of claim 1 , wherein the stiffener structure is positioned proximate to an edge of the packaging substrate.

3. The apparatus of claim 1 , wherein the stiffener structure is a frame that runs along a border of the packaging substrate.

4. The apparatus of claim 1 , wherein the stiffener structure comprises copper, aluminum, silver, or a combination thereof.

5. The apparatus of claim 1 , wherein a coefficient of thermal expansion of the stiffener structure is substantially equal to a coefficient of thermal expansion of the packaging substrate.

6. The apparatus of claim 1 , wherein the multiple semiconductor devices further define a second path along the packaging substrate between a second pair of the multiple semiconductor devices, the apparatus further comprising a second stiffener structure coupled to the packaging substrate and positioned with a longitudinal axis of the second stiffener structure being perpendicular to the second path.

7. The apparatus of claim 1 , further comprising:

at least one electrode within the packaging substrate coupled to the stiffener structure.

8. A method comprising:

attaching a first semiconductor device to a packaging substrate, wherein the packaging substrate is a redistribution layer, and wherein the redistribution layer includes a copper fanout structure positioned in a molding compound;

attaching a second semiconductor device to the packaging substrate, the first semiconductor device and the second semiconductor device defining a path therebetween along the packaging substrate;

attaching a stiffener structure to the packaging substrate with a longitudinal axis of the stiffener structure being perpendicular to the path.

9. The method of claim 8 , wherein the stiffener structure is attached proximate to an edge of the packaging substrate.

10. The method of claim 8 , wherein the stiffener structure is a frame attached along a border of the packaging substrate.

11. The method of claim 8 , wherein the stiffener structure comprises copper, aluminum, silver, or a combination thereof.

12. The method of claim 8 , further comprising selecting a material of the stiffener structure to match a coefficient of thermal expansion of the packaging substrate.

13. The method of claim 8 , further comprising:

attaching at least one additional semiconductor device to the packaging substrate, the at least one additional semiconductor device and the first semiconductor device defining an additional path therebetween along the packaging substrate; and

attaching at least one additional stiffener structure to the packaging substrate with a longitudinal axis of the at least one additional stiffener structure being perpendicular to the additional path.

14. The method of claim 8 , further comprising:

electrically coupling the stiffener structure to at least one electrode within the packaging substrate.

15. An apparatus comprising:

a redistribution layer substrate having a copper fanout structure positioned in a molding compound;

multiple semiconductor devices attached to the redistribution layer substrate, the multiple semiconductor devices defining a path along the redistribution layer substrate between a pair of the multiple semiconductor devices; and

a copper stiffener structure coupled to the redistribution layer substrate and positioned with a longitudinal axis of the copper stiffener structure being perpendicular to the path.

16. The apparatus of claim 15 , further comprising:

at least one electrode within the redistribution layer substrate and coupled to the copper stiffener structure.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2018
From: LIN, JING CHENG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047356/0692 →