IP Library Granted Patent US 10,852,953
Granted Patent B2
US 10,852,953 · App. 16/170,423 · Granted Dec 1, 2020

Dynamic temperature compensation in a memory component

Inventors: Larry J. Koudele (Erie, CO); Bruce A. Liikanen (Berthoud, CO); Steve Kientz (Westminster, CO)
Assignee: Micron Technology, Inc.
G06F3/0614G06F3/0653G06F3/0673G11C7/04G11C16/3459G11C29/028
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Quick Facts
Patent No.
US 10,852,953
App. No.
16/170,423
Granted
Dec 1, 2020
Kind
B2
Abstract

A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.

Claims (43)

1. A system, comprising:

a memory component having a register corresponding to a memory operation on a memory cell of the memory component; and

a processing device, operatively coupled with the memory component, to:

determine a dynamic temperature compensation trim for use in temperature compensating the memory operation, the determining of the dynamic temperature compensation trim being based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell, and

modify the register based on the dynamic temperature compensation trim,

wherein the in-service data includes at least one of read level calibration data or program verify level calibration data, where the program verify level calibration data checks a write operation voltage level.

2. The system of claim 1 , wherein the processing device adjusts a gate voltage level applied to the memory cell based on the dynamic temperature compensation trim.

3. The system of claim 1 , wherein the register is modified based on the temperature of the memory component in response to the memory operation being performed.

4. The system of claim 1 , wherein the register is modified based on a predetermined change in the temperature of the memory component subsequent to a prior modification of the register.

5. The system of claim 1 , wherein the memory operation is one of a read operation or a program verify operation performed on the memory cell,

wherein the memory cell belongs to a word line group of the memory component, and

wherein the dynamic temperature compensation trim corresponds to memory cells of the word line group.

6. The system of claim 1 , wherein the dynamic temperature compensation trim is based on a temperature subrange selected from a plurality of temperature subranges,

wherein the selection of the temperature subrange is based on a temperature of the memory component, and

wherein the temperature subrange covers at least a portion of an operating temperature range of the memory component.

7. The system of claim 6 , wherein the dynamic temperature compensation trim for each temperature subrange is a predetermined value corresponding to a representative temperature within the respective temperature subrange.

8. A method, comprising:

determining a dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory cell of a memory component, the determining of the dynamic temperature compensation trim based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell; and

modifying a register corresponding to the memory operation on the memory cell based on the dynamic temperature compensation trim,

wherein the in-service data includes at least one of read level calibration data or program verify level calibration data, where the program verify level calibration data checks a write operation voltage level.

9. The method of claim 8 , further comprising:

adjusting a gate voltage level applied to the memory cell based on the dynamic temperature compensation trim.

10. The method of claim 8 , wherein the register is modified based on the temperature of the memory component each time the memory operation is performed.

11. The method of claim 8 , wherein the register is modified based on a predetermined change in the temperature of the memory component subsequent to a prior modification of the register.

12. The method of claim 8 , wherein the memory operation is one of a read operation or a program verify operation performed on the memory cell, wherein the memory cell belongs to a word line group of the memory component, and wherein the dynamic temperature compensation trim corresponds to memory cells of the word line group.

13. The method of claim 8 , wherein the dynamic temperature compensation trim is based on a temperature subrange selected from a plurality of temperature subranges,

wherein the selection of the temperature subrange is based on a temperature of the memory component, and

wherein the temperature subrange covers at least a portion of an operating temperature range of the memory component.

14. The method of claim 13 , wherein the dynamic temperature compensation trim for each temperature subrange is a predetermined value corresponding to a representative temperature within the respective temperature subrange.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

determine a dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory cell of a memory component, the determining of the dynamic temperature compensation trim based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell; and

modify a register corresponding to the memory operation on the memory cell based on the dynamic temperature compensation trim,

wherein the in-service data includes at least one of read level calibration data or program verify level calibration data, where the program verify level calibration data checks a write operation voltage level.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the instructions further cause the processing device to:

adjust a gate voltage level applied to the memory cell based on the dynamic temperature compensation trim.

17. The non-transitory computer-readable storage medium of claim 15 , wherein the register is modified based on the temperature of the memory component each time the memory operation is performed.

18. The non-transitory computer-readable storage medium of claim 15 , wherein the register is modified based on a predetermined change in the temperature of the memory component subsequent to a prior modification of the register.

19. The non-transitory computer-readable storage medium of claim 15 , wherein the memory operation is one of a read operation or a program verify operation performed on the memory cell,

wherein the memory cell belongs to a word line group of the memory component, and

wherein the dynamic temperature compensation trim corresponds to memory cells of the word line group.

20. The non-transitory computer-readable storage medium of claim 15 , wherein the dynamic temperature compensation trim is based on a temperature subrange selected from a plurality of temperature subranges,

wherein the selection of the temperature subrange is based on a temperature of the memory component, and

wherein the temperature subrange covers at least a portion of an operating temperature range of the memory component.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2018
From: KOUDELE, LARRY J.; LIIKANEN, BRUCE A.; KIENTZ, STEVE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047310/0236 →