Apparatuses and methods for performing logical operations using sensing circuitry

1. A memory device, comprising:

an array of memory cells coupled to sensing circuitry; and

control circuitry configured to operate the array and sensing circuitry to perform logical operations;

wherein the sensing circuitry comprises:

a sense amplifier coupled to a pair of complementary sense lines corresponding to a column of the array; and

a compute component coupled to the sense amplifier and comprising a dynamic latch; and

wherein the control circuitry is configured to:

activate a selected logical operation control signal corresponding to a selected logical operation;

wherein activation of the selected logical operation control signal causes a result of the selected logical operation between a data value residing in the dynamic latch and a data value residing in a latch of the sense amplifier to be stored initially in the latch of the sense amplifier by overwriting the data value residing in the latch of the sense amplifier or leaving the data value residing in the latch of the sense amplifier unchanged depending on the selected logical operation; and

wherein the compute component comprises:

a first source/drain region of a first transistor coupled to a first one of the pair of complementary sense lines and directly coupled to a first source/drain region of a first load transistor; and

a first source/drain region of a second transistor coupled to a second one of the pair of complementary sense lines and directly coupled to a first source/drain region of a second load transistor; and

wherein, prior to activating the selected logical operation control signal, the load transistor is enabled to transfer a data value residing in the latch of the sense amplifier to the dynamic latch.

2. The memory device of claim 1 , wherein the compute component is formed on pitch with memory cells of the array.

3. The memory device of claim 1 , wherein the control circuitry is configured to perform the selected logical operation without transferring data values from the dynamic latch to a host coupled to the memory device.

4. The memory device of claim 3 , wherein the control circuitry is configured to perform the selected logical operation without transferring data values from the latch of the sense amplifier to the host.

5. The memory device of claim 1 , wherein the control circuitry is configured to perform the selected logical operation without transferring data values from the latch of the sense amplifier or from the dynamic latch to the control circuitry.

6. The memory device of claim 1 , wherein the compute component further comprises a static latch coupled to the dynamic latch.

7. The memory device of claim 1 , wherein the dynamic latch of the compute component is the only latch of the compute component.

8. The memory device of claim 7 , wherein the latch of the sense amplifier is the only latch of the sense amplifier.

9. The memory device of claim 8 , wherein:

prior to activating the selected logical operation control signal, the data value residing in the dynamic latch corresponds to a first input of the selected logical operation and the data value residing in the latch of the sense amplifier corresponds to a second input of the selected logical operation; and

subsequent to activating the selected logical operation control signal, the result of the selected logical operation resides in the latch of the sense amplifier.

10. A memory device, comprising:

an array of memory cells coupled to sensing circuitry; and

control circuitry configured to operate the array and sensing circuitry to perform logical operations;

wherein the sensing circuitry comprises:

a sense amplifier coupled to a pair of complementary sense lines corresponding to a column of the array; and

a compute component coupled to the sense amplifier and comprising a dynamic latch; and

wherein the control circuitry is configured to:

activate a selected logical operation control signal corresponding to a selected logical operation;

wherein activation of the selected logical operation control signal causes a result of the selected logical operation between a data value residing in the dynamic latch and a data value residing in a latch of the sense amplifier to be stored initially in the latch of the sense amplifier by overwriting the data value residing in the latch of the sense amplifier or leaving the data value residing in the latch of the sense amplifier unchanged depending on the selected logical operation; and

wherein the compute component comprises:

a first source/drain region of a first transistor coupled to a first one of the pair of complementary sense lines and to a first source/drain region of a first load transistor;

a first source/drain region of a second transistor coupled to a second one of the pair of complementary sense lines and to a first source/drain region of a second load transistor;

a second source/drain region of the first transistor coupled to a first source/drain region of a first dynamic latch transistor; and

a second source/drain region of the second transistor coupled to a first source/drain region of a second dynamic latch transistor.

11. The memory device of claim 10 , wherein the dynamic latch of the compute component is the only latch of the compute component.

12. The memory device of claim 10 , wherein the compute component further comprises a static latch coupled to the dynamic latch.

13. The memory device of claim 10 , wherein the selected logical operation control signal is one of a plurality of logical operation control signals including at least a first control signal activated to perform a logical AND operation and a second control signal activated to perform a logical OR operation.

14. The memory device of claim 10 , wherein the compute component serves as an accumulator.

15. The memory device of claim 10 , wherein the compute component further comprises:

a first invert transistor coupled to the first dynamic latch transistor; and

a second invert transistor coupled to the second dynamic latch transistor.

16. The memory device of claim 15 , wherein the first invert transistor and the second invert transistor are each coupled to the first load transistor and to the second load transistor.

17. A memory device, comprising:

an array of memory cells coupled to sensing circuitry; and

control circuitry configured to operate the array and sensing circuitry to perform logical operations;

wherein the sensing circuitry comprises:

a sense amplifier coupled to a pair of complementary sense lines corresponding to a column of the array; and

a compute component coupled to the sense amplifier and comprising a dynamic latch; and

wherein the control circuitry is configured to:

activate a selected logical operation control signal corresponding to a selected logical operation;

wherein activation of the selected logical operation control signal causes a result of the selected logical operation between a data value residing in the dynamic latch and a data value residing in a latch of the sense amplifier to be stored initially in the latch of the sense amplifier by overwriting the data value residing in the latch of the sense amplifier or leaving the data value residing in the latch of the sense amplifier unchanged depending on the selected logical operation; and

wherein the compute component comprises:

a source/drain region of a first dynamic latch transistor coupled to a first one of the pair of complementary sense lines;

a source/drain region of a second dynamic latch transistor coupled to a second one of the pair of complementary sense lines;

a gate of the first dynamic latch transistor coupled to a source/drain region of a load transistor;

a gate of the second dynamic latch transistor coupled to a source/drain region of a different load transistor; and

a gate of the first load transistor coupled to a gate of the different load transistor.

18. The memory device of claim 17 , wherein the compute component further comprises:

a first pull-down transistor having a first source/drain region coupled to the first dynamic latch transistor; and

a second pull-down transistor having a first source/drain region coupled to the second dynamic latch transistor.

19. The memory device of claim 18 , wherein the compute component further comprises:

a third pull-down transistor having a first source/drain region coupled to a second source/drain region of the first pull-down transistor; and

a fourth pull-down transistor having a first source/drain region coupled to a second source/drain region of the second pull-down transistor.

20. The memory device of claim 18 , wherein the second source/drain region of the first pull-down transistor is coupled to the second source/drain region of the second pull-down transistor.