Dynamic programing of valley margins of a memory cell

1. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

determine a plurality of difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component;

scale each of the plurality of difference error counts by a respective scale factor of a plurality of scale factors; and

adjust valley margins of the memory cell in accordance with the plurality of scaled difference error counts.

2. The system of claim 1 , wherein to adjust the valley margins of the memory cell in accordance with the plurality of scaled difference error counts, the processing device is to:

perform a dynamic program targeting (DPT) operation on the memory cell to calibrate one or more program-verify (PV) targets associated with the programming distributions based on the scaled difference error counts.

3. The system of claim 2 , wherein the DPT operation converges respective scaled difference error counts of the plurality of scaled difference error counts for a particular logical page type of the memory cell to a convergence value.

4. The system of claim 2 , wherein to perform a dynamic program targeting (DPT) operation on the memory cell to calibrate the one or more PV targets associated with the programming distributions, the processing device is to:

determine a first adjustment amount of a first PV target and a second adjustment amount of a second PV target that converges at least two of the scaled difference error counts to a convergence value;

adjust the first PV target by the first adjustment amount; and

adjust the second PV target by the second adjustment amount.

5. The system of claim 2 , wherein to calibrate the one or more PV targets associated with the programming distributions, the processing device is to:

determine a net-zero adjustment to at least two of the PV targets associated with the programming distributions based on the at least two of the scaled difference error counts; and

adjust the at least two PV targets according to the net-zero adjustment.

6. The system of claim 1 , wherein the difference error is inversely proportional to the valley margins.

7. The system of claim 1 , wherein to determine the plurality of difference error counts for the difference error, for each of the plurality of difference error counts the processing device to:

perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate read level thresholds between the programming distributions.

8. The system of claim 7 , wherein to perform the cRLC operation on the memory cell to calibrate the read level thresholds between the programming distributions, the processing device is to:

adjust the read level thresholds to a center value that results in a lowest bit error rate.

9. The system of claim 8 , wherein to perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate read level thresholds between the programming distributions, the processing device is further to:

sample the center value, a positive offset value, and a negative offset value between the programming distributions of the memory cell, wherein a difference error count of the plurality of difference error counts is determined using the center value, the positive offset value, and the negative offset value.

10. The system of claim 9 , wherein for a particular logical page type the respective positive offset values and negative offset values are of an equal magnitude.

11. The system of claim 9 , wherein to perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate read level thresholds between the programming distributions, the processing device is further to:

calculate a mean of the positive offset value and the negative offset value less the center value to determine each of the plurality of difference error counts.

12. The system of claim 1 , wherein the valley margins of the memory cell are adjusted dynamically during operation of the memory component.

13. The system of claim 1 , wherein the memory component comprises a block, the block comprising a plurality of memory cells organized in a plurality of wordline groups, wherein valley margins of a first wordline group of the plurality of wordline groups are adjusted independently from valley margins of a second wordline group of the plurality of wordline groups.

14. A method comprising:

determining a plurality of difference error counts for a difference error that is indicative of a margin fora valley that is located between programming distributions of a memory cell of a memory component;

scaling each of the plurality of difference error counts by a respective scale factor of a plurality of scale factors; and

adjusting, by a processing device, valley margins of the memory cell in accordance with the plurality of scaled difference error counts.

15. The method of claim 14 , wherein adjusting the valley margins of the memory cell in accordance with the plurality of scaled difference error counts, the method further comprising:

performing a dynamic program targeting (DPT) operation on the memory cell to calibrate one or more program-verify (PV) targets associated with the programming distributions based on the scaled difference error counts.

16. The method of claim 15 , wherein the DPT operation converges respective scaled difference error counts of the plurality of scaled difference error counts for a particular logical page type of the memory cell to a convergence value.

17. The method of claim 14 , wherein determining the plurality of difference error counts for the difference error, for each of the plurality of difference error counts the method comprising:

performing a continuous read level calibration (cRLC) operation on the memory cell to calibrate read level thresholds between the programming distributions so that the read level thresholds are adjusted to a center value that results in a lowest bit error rate.

18. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to:

determine a plurality of difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of a memory component;

scale each of the plurality of difference error counts by a respective scale factor of a plurality of scale factors; and

adjust, by the processing device, valley margins of the memory cell in accordance with the plurality of scaled difference error counts.

19. The non-transitory computer-readable medium of claim 18 , wherein to adjust the valley margins of the memory cell in accordance with the plurality of scaled difference error counts, the processing device to:

perform a dynamic program targeting (DPT) operation on the memory cell to calibrate one or more program-verify (PV) targets associated with the programming distributions based on the scaled difference error counts, wherein the DPT operation converges respective scaled difference error counts of the plurality of scaled difference error counts for a particular logical page type of the memory cell to a convergence value.

20. The non-transitory computer-readable medium of claim 18 , wherein to determine the plurality of difference error counts for the difference error, for each of the plurality of difference error counts, the processing device to:

perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate read level thresholds between the programming distributions so that the read level thresholds are adjusted to a center value that results in a lowest bit error rate.