IP Library › Granted Patent US 10,741,252

Granted Patent B2

US 10,741,252 · App. 16/223,305 · Granted Aug 11, 2020

Apparatus and methods for programming memory cells using multi-step programming pulses

Inventor: Eric N. Lee (San Jose, CA)

Assignee: Micron Technology, Inc.

G11C16/10 G11C16/0483 G11C16/3459 G11C11/5628 G11C11/5671 G11C2211/5621

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Quick Facts

Patent No.: US 10,741,252
App. No.: 16/223,305
Granted: Aug 11, 2020
Kind: B2

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Abstract

Methods of operating a memory, and memory configured to perform similar methods, might include applying a particular multi-step programming pulse to a selected access line of a programming operation, and applying a next subsequent multi-step programming pulse to the selected access line, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level different than the first voltage level, and wherein the next subsequent multi-step programming pulse has a first step having a third voltage level and a second step having a fourth voltage level different than the third voltage level and higher than the first voltage level.

Claims (100)

1. A memory, comprising:

an array of memory cells; and

a controller configured to access the array of memory cells;

wherein the controller is further configured to:

for a plurality of memory cells of the array of memory cells selected for programming during a programming operation, wherein each memory cell of the plurality of memory cells has a respective intended data state of a plurality of intended data states for the programming operation, determine a first subset of memory cells of the plurality of memory cells, wherein each memory cell of the first subset of memory cells is activated in response to a respective intermediate verify voltage corresponding to its respective intended data state, and determine a second subset of memory cells of the plurality of memory cells, wherein each memory cell of the second subset of memory cells is activated in response to a respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state;

apply a particular multi-step programming pulse to a selected access line of the programming operation, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level lower than the first voltage level, and wherein the selected access line is connected to the plurality of memory cells;

enable the first subset of memory cells for programming while applying the first step of the particular multi-step programming pulse;

inhibit the second subset of memory cells from programming while applying the first step of the particular multi-step programming pulse and enable the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse; and

wherein, for each intended data state of the plurality of intended data states, the respective intermediate verify voltage for that intended data state is lower than the respective target verify voltage for that intended data state.

2. The memory of claim 1 , wherein the controller is further configured to:

determine a third subset of memory cells of the plurality of memory cells, wherein each memory cell of the third subset of memory cells is activated in response to the respective intermediate verify voltage corresponding to its respective intended data state; and

determine a fourth subset of memory cells of the plurality of memory cells, wherein each memory cell of the fourth subset of memory cells is activated in response to the respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state.

3. The memory of claim 1 , wherein the controller being configured to enable the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse comprises the controller being configured to partially enable a particular memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse and the controller being configured to fully enable a different memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse.

4. The memory of claim 2 , wherein the controller is further configured to:

enable the third subset of memory cells for programming while applying the first step of the next subsequent multi-step programming pulse;

inhibit the fourth subset of memory cells from programming while applying the first step of the next subsequent multi-step programming pulse; and

enable the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

5. The memory of claim 1 , wherein the controller is further configured to:

enable the first subset of memory cells for programming before applying the first step of the particular multi-step programming pulse; and

enable the second subset of memory cells for programming before applying the second step of the particular multi-step programming pulse.

6. The memory of claim 5 , wherein the controller is further configured to:

enable the first subset of memory cells for programming while applying the second step of the particular multi-step programming pulse.

7. The memory of claim 1 , wherein a voltage difference between the third voltage level and the fourth voltage level is substantially equal to a voltage difference between the first voltage level and the second voltage level.

8. The memory of claim 1 , wherein a voltage difference between the third voltage level and the first voltage level is substantially equal to two times the voltage difference between the first voltage level and the second voltage level.

9. The memory of claim 2 , wherein memory cells of the second subset of memory cells contain memory cells deemed to be nearer their respective intended data states than memory cells of the first subset of memory cells.

10. The memory of claim 9 , wherein memory cells of the fourth subset of memory cells contain memory cells deemed to be nearer their respective intended data states than memory cells of the third subset of memory cells.

11. The memory of claim 1 , wherein the controller is further configured to apply the second step of the particular multi-step programming pulse prior to applying the first step of the particular multi-step programming pulse, and to apply the second step of the next subsequent multi-step programming pulse prior to the first step of the next subsequent multi-step programming pulse.

12. A method of operating a memory, comprising:

for a plurality of memory cells of the array of memory cells selected for programming during a programming operation, wherein each memory cell of the plurality of memory cells has a respective intended data state of a plurality of intended data states for the programming operation, determining a first subset of memory cells of the plurality of memory cells, wherein each memory cell of the first subset of memory cells is activated in response to a respective intermediate verify voltage corresponding to its respective intended data state, and determining a second subset of memory cells of the plurality of memory cells, wherein each memory cell of the second subset of memory cells is activated in response to a respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state;

applying a particular multi-step programming pulse to a selected access line of the programming operation, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level lower than the first voltage level, and wherein the selected access line is connected to the plurality of memory cells;

enabling the first subset of memory cells for programming while applying the first step of the particular multi-step programming pulse;

inhibiting the second subset of memory cells from programming while applying the first step of the particular multi-step programming pulse and enabling the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse; and

13. The method of claim 12 , further comprising:

determining a third subset of memory cells of the plurality of memory cells, wherein each memory cell of the third subset of memory cells is activated in response to the respective intermediate verify voltage corresponding to its respective intended data state; and

determining a fourth subset of memory cells of the plurality of memory cells, wherein each memory cell of the fourth subset of memory cells is activated in response to the respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state.

14. The method of claim 12 , further comprising:

performing a verify operation after applying the particular multi-step programming pulse and prior to applying the next subsequent multi-step programming pulse.

15. The method of claim 14 , wherein performing the verify operation comprises determining which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage higher than the target verify voltage corresponding to their respective intended data states, which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than the target verify voltage corresponding to their respective intended data states and higher than the intermediate verify voltage corresponding to their respective intended data states, and which memory cells of the first subset of memory cells are deemed to have a threshold voltage lower than the intermediate verify voltage corresponding to their respective intended data states.

16. The method of claim 15 , further comprising:

enabling for programming those memory cells of the first subset of memory cells deemed to have a threshold voltage lower than the intermediate verify voltage corresponding to their respective intended data states while applying the first step of the next subsequent multi-step programming pulse;

enabling for programming those memory cells of the first subset of memory cells and the second subset of memory cells deemed to have a threshold voltage lower than the target verify voltage corresponding to their respective intended data states and higher than the intermediate verify voltage corresponding to their respective intended data states while applying the second step of the next subsequent multi-step programming pulse; and

inhibiting from programming those memory cells of the first subset of memory cells and the second subset of memory cells deemed to have a threshold voltage higher than the target verify voltage corresponding to their respective intended data states while applying the second step of the next subsequent multi-step programming pulse.

17. The method of claim 15 , wherein performing the verify operation further comprises determining which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than or equal to the target verify voltage corresponding to their respective intended data states, and which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than or equal to the intermediate verify voltage corresponding to their respective intended data states.

18. The method of claim 12 , wherein enabling the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse comprises fully enabling a particular memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse, and partially enabling a different memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse.

19. The method of claim 13 , further comprising:

enabling the third subset of memory cells for programming while applying the first step of the next subsequent multi-step programming pulse;

inhibiting the fourth subset of memory cells from programming while applying the first step of the next subsequent multi-step programming pulse; and

enabling the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

20. A memory, comprising:

an array of memory cells; and

a controller configured to access the array of memory cells;

wherein the controller is further configured to:

apply a particular multi-step programming pulse to a selected access line of the programming operation, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level different than the first voltage level, wherein a voltage difference between the first voltage level and the second voltage level has a particular value, and wherein the selected access line is connected to the plurality of memory cells;

enable the first subset of memory cells for programming while applying the first step of the particular multi-step programming pulse;

apply a next subsequent multi-step programming pulse to the selected access line, wherein the next subsequent multi-step programming pulse has a first step having a third voltage level and a second step having a fourth voltage level different than the third voltage level, and wherein a voltage difference between the third voltage level and the first voltage level is substantially equal to two times the particular value, and a voltage difference between the fourth voltage level and the second voltage level is substantially equal to two times the particular value;

21. The memory of claim 20 , wherein the controller is further configured to:

determine a third subset of memory cells of the plurality of memory cells after applying the particular multi-step programming pulse, wherein each memory cell of the third subset of memory cells is activated in response to the respective intermediate verify voltage corresponding to its respective intended data state; and

determine a fourth subset of memory cells of the plurality of memory cells after applying the particular multi-step programming pulse, wherein each memory cell of the fourth subset of memory cells is activated in response to the respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data states;

enable the third subset of memory cells for programming while applying the first step of the next subsequent multi-step programming pulse;

inhibit the fourth subset of memory cells from programming while applying the first step of the next subsequent multi-step programming pulse; and

enable the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

22. The memory of claim 21 , wherein the controller being configured to enable the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse comprises the controller being configured to partially enable a particular memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse and the controller being configured to fully enable a different memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse, and wherein the controller being configured to enable the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse comprises the controller being configured to partially enable a particular memory cell of the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse and the controller being configured to fully enable a different memory cell of the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

23. The memory of claim 21 , wherein the controller is further configured to:

enable the first subset of memory cells for programming before applying the first step of the particular multi-step programming pulse;

enable the second subset of memory cells for programming before applying the second step of the particular multi-step programming pulse;

enable the third subset of memory cells for programming before applying the first step of the next subsequent multi-step programming pulse; and

enable the fourth subset of memory cells for programming before applying the second step of the next subsequent multi-step programming pulse.

24. The memory of claim 23 , wherein the controller is further configured to:

enable the first subset of memory cells for programming while applying the second step of the particular multi-step programming pulse; and

enable the third subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

25. The memory of claim 20 , wherein second voltage level is lower than the first voltage level, and wherein the fourth voltage level is lower than the third voltage level.

26. The memory of claim 21 , wherein memory cells of the second subset of memory cells contain memory cells deemed to be nearer their respective intended data states than memory cells of the first subset of memory cells, and wherein memory cells of the fourth subset of memory cells contain memory cells deemed to be nearer their respective intended data states than memory cells of the third subset of memory cells.

27. A method of operating a memory, comprising:

for a plurality of memory cells of the array of memory cells selected for programming during a programming operation, wherein each memory cell of the plurality of memory cells has a respective intended data state of a plurality of intended data states for the programming operation, determining a first subset of memory cells of the plurality of memory cells, wherein each memory cell of the first subset of memory cells is activated in response to a respective intermediate verify voltage corresponding to its respective intended data state, and determining a second subset of memory cells of the plurality of memory cells, wherein each memory cell of the second subset of memory cells is activated in response to a respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state;

applying a particular multi-step programming pulse to a selected access line of the programming operation, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level different than the first voltage level, wherein a voltage difference between the first voltage level and the second voltage level has a particular value, and wherein the selected access line is connected to the plurality of memory cells;

enabling the first subset of memory cells for programming while applying the first step of the particular multi-step programming pulse;

applying a next subsequent multi-step programming pulse to the selected access line, wherein the next subsequent multi-step programming pulse has a first step having a third voltage level and a second step having a fourth voltage level different than the third voltage level, and wherein a voltage difference between the third voltage level and the first voltage level is substantially equal to two times the particular value, and a voltage difference between the fourth voltage level and the second voltage level is substantially equal to two times the particular value;

28. The method of claim 27 , further comprising:

determining a third subset of memory cells of the plurality of memory cells after applying the particular multi-step programming pulse, wherein each memory cell of the third subset of memory cells is activated in response to the respective intermediate verify voltage corresponding to its respective intended data state;

determining a fourth subset of memory cells of the plurality of memory cells after applying the particular multi-step programming pulse, wherein each memory cell of the fourth subset of memo r cells is activated in response to the respective target verify voltage corresponding to its respective intended data state and deactivated in response to the respective intermediate verify voltage corresponding to its respective intended data state;

enabling the third subset of memory cells for programming while applying the first step of the next subsequent multi-step programming pulse;

inhibiting the fourth subset of memory cells from programming while applying the first step of the next subsequent multi-step programming pulse; and

enabling the fourth subset of memory cells for programming while applying the second step of the next subsequent multi-step programming pulse.

29. The method of claim 28 , further comprising:

performing a verify operation after applying the particular multi-step programming pulse and prior to applying the next subsequent multi-step programming pulse.

30. The method of claim 29 , wherein performing the verify operation comprises determining which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage higher than the target verify voltage corresponding to their respective intended data states, which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than the target verify voltage corresponding to their respective intended data states and higher than the intermediate verify voltage corresponding to their respective intended data states, and which memory cells of the first subset of memory cells are deemed to have a threshold voltage lower than the intermediate verify voltage corresponding to their respective intended data states.

31. The method of claim 30 , further comprising:

32. The method of claim 30 , wherein performing the verify operation further comprises determining which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than or equal to the target verify voltage corresponding to their respective intended data states, and which memory cells of the first subset of memory cells and of the second subset of memory cells are deemed to have a threshold voltage lower than or equal to the intermediate verify voltage corresponding to their respective intended data states.

33. The method of claim 28 , wherein enabling the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse comprises fully enabling a particular memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse, and partially enabling a different memory cell of the second subset of memory cells for programming while applying the second step of the particular multi-step programming pulse.

Assignments (5)

RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019

From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT

To: MICRON TECHNOLOGY, INC.

Reel/Frame 051041/0317 →

RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019

From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT

To: MICRON TECHNOLOGY, INC.

Reel/Frame 050724/0392 →

SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019

From: MICRON TECHNOLOGY, INC.

To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT