IP Library Granted Patent US 11,081,460
Granted Patent B2
US 11,081,460 · App. 16/236,237 · Granted Aug 3, 2021

Methods and systems for manufacturing pillar structures on semiconductor devices

Inventors: Suresh Yeruva (Boise, ID); Owen R. Fay (Meridian, ID); Sameer S. Vadhavkar (Boise, ID); Adriel Jebin Jacob Jebaraj (Boise, ID); Wayne H. Huang (Boise, ID)
Assignee: Micron Technology, Inc.
H01L24/14H01L24/11H01L24/13H01L2224/1146H01L2224/11614H01L2224/13083H01L2224/13111H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/14517H01L2924/35121
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Quick Facts
Patent No.
US 11,081,460
App. No.
16/236,237
Granted
Aug 3, 2021
Kind
B2
Abstract

A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

Claims (40)

1. A method of manufacturing a semiconductor device, the semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface, the method comprising:

applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate;

forming a plurality of pillars, wherein one or more of the pillars are positioned entirely over a portion of the passivation material, wherein forming the plurality of pillars comprises:

depositing a first material onto a portion of the seed layer, and

depositing a second material onto the first material; and

etching the seed layer to remove the conductive material from the passivation material between the plurality of pillars and to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars;

wherein a cross-sectional area of the seed layer of the one or more pillars positioned entirely over a portion of the passivation material, as measured parallel to the first surface of the conductive substrate, is less than the cross-sectional area of the first material as measured parallel to the first surface of the conductive substrate.

2. The method of claim 1 , further comprising forming a mask structure on the seed layer, the mask structure having a plurality of through holes, wherein the plurality of pillars are formed in the plurality of through holes of the mask structure.

3. The method of claim 2 , comprising removing the mask structure from the seed layer prior to etching the seed layer.

4. The method of claim 2 , wherein the plurality of through holes comprise a first through hole having a first width as measured parallel to the first surface of the conductive substrate and a second through hole having a second width greater than the first width.

5. The method of claim 4 , wherein the first through hole is positioned over a portion of the passivation material and the second through hole is positioned over a portion of the conductive substrate not covered by the passivation material.

6. The method of claim 1 , wherein the cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate, as measured parallel to the first surface of the conductive substrate, is less than or equal to ½ of the cross-sectional area of the second material as measured parallel to the first surface of the conductive substrate.

7. The method of claim 1 , wherein the cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate, as measured parallel to the first surface of the conductive substrate, is less than or equal to ¼ of the cross-sectional area of the second material as measured parallel to the first surface of the conductive substrate.

8. The method of claim 1 , wherein the seed layer comprises copper.

9. The method of claim 1 , wherein the first material comprises nickel.

10. The method of claim 1 , wherein the second material comprises tin-silver.

11. A method of manufacturing a semiconductor device, the semiconductor device having a conductive substrate having a first surface partially covered by a passivation material and a second surface opposite the first surface, the method comprising:

covering at least a portion of the first surface and the passivation material with a layer of conductive material, the layer of conductive material having a first side opposite the conductive substrate;

depositing a first material onto the layer of conductive material thereby forming bases for a first pillar and a second pillar;

depositing a second material onto the first material;

removing the layer of conductive material from portions of the passivation material and the first surface of the conductive substrate outside of the first and second pillars; and

undercutting the layer of conductive material between the layer of first material of the first pillar and the conductive substrate;

wherein the first pillar is positioned over a portion of the conductive substrate completely covered by the passivation material.

12. The method of claim 11 , further comprising undercutting the layer of conductive material between the layer of first material of the second pillar and the conductive substrate, wherein the second pillar is positioned over a portion of the conductive substrate not covered by the passivation material.

13. The method of claim 11 , further comprising forming a mask structure on the layer of conductive material, wherein the first material is deposited onto the layer of conductive material within through holes of the mask structure.

14. The method of claim 11 , wherein the first material is nickel.

15. The method of claim 14 , wherein the second material comprises tin-silver.

16. The method of claim 11 , wherein first pillar has a first width and the second pillar has a second width greater than the first width, wherein the second pillar is positioned over a portion of the conductive substrate not covered by the passivation material.

17. A method of manufacturing a semiconductor device, the method comprising:

forming a mask on a seed structure, wherein the mask has a first set of openings that expose areas of the seed structure that are electrically coupled to live circuitry on a side of the seed structure opposite the mask, and wherein the mask has a second set of openings that expose areas of the seed structure that are entirely in direct contact with a passivation material positioned between the seed structure and the live circuitry;

plating a first material onto the exposed areas of the seed structure;

depositing a second material into the openings over the first material, thereby forming a first set of pillars within the first set of opening and a second set of pillar within the second set of openings, wherein the second material is different from the first material;

removing at least a portion of the mask to expose portions of the seed structure between the pillars;

removing the exposed portions of the seed structure between the pillars; and

undercutting the seed structure on a side of the first material of the second set of pillars opposite the second material of the second set of pillars.

18. The method of claim 17 , wherein the first material comprises nickel and the second material comprises tin-silver.

19. The method of claim 17 , further comprising connecting the second material to a conductive pillar of a through-substrate via of a semiconductor die.

20. The method of claim 17 , further comprising undercutting the seed structure on a side of the first material of the first set of pillars opposite the second material of the first set of pillars.

21. The method of claim 17 wherein the seed structure on the side of the first material of the second set of pillars opposite the second material of the second set of pillars has a cross-sectional area less than ⅓ of a cross-sectional area of the first material of the second set of pillars.

22. The method of claim 17 , wherein the first set of openings include a first opening having a first width and the second set of openings include a second opening having a second width less than the first width.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2019
From: YERUVA, SURESH; FAY, OWEN R.; VADHAVKAR, SAMEER S.; JEBARAJ, ADRIEL JEBIN JACOB; HUANG, WAYNE H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050882/0749 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →