Apparatuses and methods for performing corner turn operations using sensing circuitry

1. An apparatus comprising:

a first group of memory cells coupled to a particular access line and to a plurality of sense lines;

a second group of memory cells coupled to a plurality of access lines and to one of the plurality of sense lines, wherein the particular access line is one of the plurality of access lines; and

a controller configured to cause a corner turn operation to be performed on an element stored in the first group of memory cells such that the corner turn operation results in the element being stored in the second group of memory cells;

wherein the controller is configured to cause performance of the corner turn operation by controlling sensing circuitry coupled to the plurality of sense lines to perform a plurality of logical operations using data units corresponding to the element as inputs.

2. The apparatus of claim 1 , wherein the plurality of logical operations comprises at least one of:

a number of AND operations;

a number of OR operations; and

a number of XOR operations.

3. The apparatus of claim 2 , wherein the controller is configured to cause performance of the corner turn operation by performing the plurality of logical operations without transferring data external to the sensing circuitry.

4. The apparatus of claim 2 , wherein the controller is further configured to cause performance of the corner turn operation by controlling the sensing circuitry to perform a plurality of shift operations on bit-vectors stored in the sensing circuitry.

5. The apparatus of claim 1 , wherein the apparatus comprises a memory device coupled to an external processor, and therein the controller is located on the memory device and is configured to perform the corner turn operation without transferring data to the external processor via a bus.

6. The apparatus of claim 1 , wherein the sensing circuitry comprises a plurality of sense amplifier and compute component pairs each pair corresponding to one of a respective plurality of columns of an array comprising the first and second groups of memory cells.

7. The apparatus of claim 1 , wherein the element comprises a bit-vector.

8. A method for performing a corner turn, comprising:

performing, in parallel, a plurality of corner turn operations, using a controller to control sensing circuitry, to relocate elements stored in a first format in memory cells coupled to a plurality of access lines and to a plurality of sense lines of a memory array to being stored in a second format in the memory cells,

wherein performing the plurality of corner turn operations comprises:

accessing an element stored in the first format in memory cells coupled to one of the plurality of access lines and the plurality of sense lines;

relocating the element in the second format in memory cells coupled to one of the plurality of sense lines and the plurality of access lines; and

performing a number of logical operations.

9. The method of claim 8 , wherein performing the number of logical operations comprises performing at least one of:

a number of AND operations;

a number of OR operations; and

a number of XOR operations.

10. The method of claim 8 , wherein the method includes:

storing a first of the elements in a first group of memory cells coupled to the first of the plurality of access lines and to the plurality of sense lines when in the first format; and

storing the first element in a second group of memory cells coupled to the plurality of access lines and a first of the plurality of sense lines when in the second format.

11. The method of claim 8 , wherein, when in the first format, storing a data unit of each of the elements having a same significance in memory cells coupled to a same sense line.

12. The method of claim 11 , wherein, when in the second format, storing a data unit of each of the elements having a same significance in memory cells coupled to a same access line.

13. A system, comprising:

a host configured to generate instructions; and

a memory device configured to execute instructions from the host to perform a corner turn operation, in parallel, on a first element stored in a first group of memory cells coupled to a first access line and to a plurality of first sense lines and on a second element stored in a second group of memory cells coupled to a second access line and to a plurality of second sense lines such that, subsequent to the corner turn:

the first element is stored in memory cells coupled to one of the plurality of first sense lines and a plurality of first access lines that includes the first access line; and

the second element is stored in memory cells coupled to one of the plurality of second sense lines and the plurality first access lines that includes the first access line; and

wherein the corner turn operation is performed by the memory device using sensing circuitry to perform a number of logical operations.

14. The system of claim 13 , wherein the host comprises a processing resource configured to generate the instructions.

15. The system of claim 14 , wherein the processing resource comprises one of:

a host processor; and

a controller.

16. The system of claim 13 , wherein the memory device is configured to perform logical operations on the first and second elements and provide results of the logical operation to the host via a bus.

17. The system of claim 13 , wherein the memory device comprises control circuitry configured to execute instructions received from the host.

18. The system of claim 17 , wherein the control circuitry comprises at least one of:

a sequencer; and

a state machine.

19. The system of claim 13 , wherein the host and the memory device are on a same integrated circuit.

20. The system of claim 13 , wherein the number of logical operations comprise at least one of:

a number of AND operations;

a number of OR operations; and

a number of XOR operations.