Apparatuses and methods for performing corner turn operations using sensing circuitry

1. An apparatus comprising:

a first group of memory cells coupled to an access line and a plurality of sense lines;

a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines, wherein the access line is a same access line as one of the plurality of access lines; and

a controller configured to cause a corner turn operation on an element stored in the first group of memory cells that results in the element being stored in the second group of memory cells to be performed using a sensing circuitry;

wherein the controller is configured to cause the corner turn operation by operating the first and the second groups of memory cells and the sensing circuitry to perform at least one of a number of AND operations, OR operations, XOR operations, and SHIFT operations without performing a sense line address access.

2. The apparatus of claim 1 , wherein the sensing circuitry comprises a number of transistors on pitch with a number of memory cells coupled to a number of columns of complementary sense lines corresponding to the first and second groups of memory cells.

3. The apparatus of claim 2 , wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.

4. The apparatus of claim 3 , wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

5. A method for performing a corner turn, comprising:

performing, in parallel, a plurality of corner turn operations, using a controller to control sensing circuitry, to relocate elements stored in a first format in memory cells coupled to a plurality of access lines and to a plurality of sense lines of a memory array to being stored in a second format in the memory cells,

wherein performing the plurality of corner turn operations comprises:

accessing an element stored in the first format in memory cells coupled to one of the plurality of access lines and the plurality of sense lines;

relocating the element in the second format in memory cells coupled to one of the plurality of sense lines and the plurality of access lines; and

performing at least one of a number of AND operations, OR operations, XOR operations, and SHIFT operations without performing a sense line address access.

6. The method of claim 5 , wherein the method includes performing the plurality of corner turn operations in parallel.

7. The method of claim 5 , wherein the method includes:

storing a first of the elements in a first group of memory cells coupled to the first of the plurality of access lines and to the plurality of sense lines when in the first format; and

storing the first element in a second group of memory cells coupled to the plurality of access lines and a first of the plurality of sense lines when in the second format.

8. The method of claim 5 , wherein, when in the first format, storing a first data unit of each of the elements in memory cells coupled to one of the plurality of sense lines.

9. The method of claim 8 , wherein, when in the second format, storing a first data unit of each of the elements in memory cells coupled to one of the plurality of access lines.

10. The method of claim 9 , wherein storing the first data unit comprises storing a most significant bit.

11. The method of claim 5 , wherein, when in the first format, storing a data unit of each of the elements having a same significance in memory cells coupled to a same sense line.

12. The method of claim 5 , wherein, when in the second format, storing a data unit of each of the elements having a same significance in memory cells coupled to a same access line.

13. A method for performing a corner turn, comprising:

using a controller configured to control sensing circuitry to perform a corner turn operation by performing at least one of a number of AND operations, OR operations, XOR operations, and SHIFT operations without performing a sense line address access;

wherein:

using the controller comprises:

accessing an element stored in a first group of memory cells coupled to a first access line and to a plurality of sense lines of a memory array; and

storing the element in a second group of memory cells coupled to a plurality of access lines and a first of the plurality of sense lines; and

the first access line is one of the plurality of access lines.

14. The method of claim 13 , wherein performing the plurality of corner turn operations comprises:

relocating, in parallel, first data units of each of the elements stored in memory cells coupled to a same sense line; and

storing, in parallel, first data units of each of the elements in memory cells coupled to a same access line of the plurality of access lines.

15. The method of claim 13 , wherein performing the plurality of corner turn operations comprises:

relocating, in parallel, a data unit of each of the elements with a same significance value that are stored in memory cells coupled to a same access line; and

storing, in parallel, the data unit of each of the elements in memory cells coupled to a same access line of the plurality of access lines.

16. The method of claim 15 , wherein performing the plurality of corner turn operations comprises:

relocating, in parallel, a first data unit of each of the elements stored in memory cells coupled to a first sense line; and

storing the first data unit of each of the elements in memory cells coupled to a first access line of the plurality of access lines.

17. The method of claim 16 , wherein performing the plurality of corner turn operations comprises:

relocating, in parallel, a second data unit of each of the elements stored in memory cells coupled to a second sense line; and

storing the second data unit of each of the elements in memory cells coupled to a second access line of the plurality of access lines.

18. The method of claim 13 , wherein the method comprises performing a number of the plurality of corner turn operations that correspond to a width of the elements independent of a number of the elements.

19. An apparatus, comprising:

a first group of memory cells coupled to a first access line and a plurality of sense lines configured to store a number of first elements;

a second group of memory cells coupled to a second access line and the plurality of sense lines configured to store a number of second elements; and

a controller configured to cause a plurality of corner turn operations on the number of first elements and the number of second elements to be performed using a sensing circuitry to perform at least one of a number of AND operations, OR operations, XOR operations, and SHIFT operations without performing a sense line address access;

wherein the controller is configured to:

relocate a first data unit of each of the number of first and second elements from memory cells coupled to the first access line and the second access line, respectively, to memory cells coupled to the first access line and the plurality of sense lines.

20. The apparatus of claim 19 , wherein the controller is further configured to operate the memory cells and the sensing circuitry to:

relocate a first data unit of a first element of the number of first elements stored in a memory cell coupled to a first of the plurality of access lines and a first of the plurality of sense lines; and

store the first data unit of the first element to the memory cell coupled to the first of the plurality of access lines and the first of the plurality of sense lines.

21. The apparatus of claim 20 , wherein the controller is further configured to operate the memory cells and the sensing circuitry to:

relocate a second data unit of a first element of the number of first elements stored in a memory cell coupled to a first of the plurality of access lines and a second of the plurality of sense lines; and

store the second data unit of the first element in the memory cell coupled to a second of the plurality of access lines and the first of the plurality of sense lines.

22. The apparatus of claim 19 , wherein the controller is further configured to operate the memory cells and the sensing circuitry to:

relocate a second data unit of each of the number of first and second elements in memory cells coupled to the first access line and the second access line, respectively; and

store the second data unit of each of the number of first and second elements in memory cells coupled to the second access line and the plurality of sense lines.

23. The apparatus of claim 19 , wherein the controller is further configured to operate the memory cells and the sensing circuitry to:

relocate an Nth data unit of each of the number of first and second elements stored in memory cells coupled to the first access line and the second access line, respectively; and

store the Nth data unit of each of the number of first and second elements in memory cells coupled to an Nth access line of the plurality of access lines and the plurality of sense lines.

24. An apparatus, comprising:

a group of memory cells coupled to a plurality of access lines and a plurality of sense lines configured to store a number of elements; and

a controller configured to cause, in parallel, a plurality of corner turn operations on the number of elements stored in the group of memory cells to relocate the number of elements from being stored in a first format in the group of memory cells to being stored in a second format in the group of memory cells to be performed using sensing circuitry to perform at least one of a number of AND operations, OR operations, XOR operations, and SHIFT operations without performing a sense line address access;

wherein:

the first format comprises each of the elements being stored in the group of the memory cells coupled to one of the plurality of access lines and to the plurality of sense lines; and

the second format comprises each of the elements being stored in the group of the memory cells coupled to the plurality of access lines and to one of the plurality of sense lines.

25. The apparatus of claim 24 , wherein the controller is configured to relocate the elements by storing a most significant bit of each of the elements in memory cells coupled to one of the plurality of access lines and the plurality of sense lines when in the second format.