Patent Assignment
Reel/Frame 039841/0207
Supplement No. 1 to Patent Security Agreement
Recorded: 2016-08-26
Pages: 15
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2016-07-25
Assignee
U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
800 NICOLLET MALL, MINNEAPOLIS, MINNESOTA, 55402
Covered Properties
(167)
Apparatus and Method for Imager Device Color Calibration Using Spectral Light Source
Semiconductor Constructions
Passing Access Line Structure in a Memory Device
Methods of Forming Charge-Trapping Regions
Accessing Memory Cells in Parallel in a Cross-Point Array
Apparatuses and Methods for Shifting Data During a Masked Write to a Buffer
Patent:
9,570,125 →
Application:
15/070,670 →
Apparatus and Methods for Through Substrate via Test
Methods and Apparatuses Including a String of Memory Cells Having a First Select Transistor Coupled to a Second Select Transistor
Partial Page Memory Operations
Invert Operations Using Sensing Circuitry
Apparatuses and Methods for Performing Corner Turn Operations Using Sensing Circuitry
Patent:
9,659,605 →
Application:
15/133,861 →
Apparatuses and Methods for Performing Corner Turn Operations Using Sensing Circuitry
Multi-Level Hierarchical Routing Matrices for Pattern-Recognition Processors
Solid State Optoelectronic Device with Preformed Metal Support Substrate
Signal Delivery in Stacked Device
Apparatuses and Methods for Detecting Frequency Ranges Corresponding to Signal Delays of Conductive Vias
Patent:
9,722,588 →
Application:
15/138,042 →
Apparatuses and Methods for Comparing a Current Representative of a Number of Failing Memory Cells
Methods and Apparatuses Including Command Delay Adjustment Circuit
Apparatuses and Methods for Adjusting a Delay of a Command Signal Path
Patent:
9,601,170 →
Application:
15/139,120 →
Data Caching for Ferroelectric Memory
Signal Driver Circuit Having Adjustable Output Voltage for a High Logic Level Output Signal
Secure Shared Key Sharing Systems and Methods
Charge Sharing Between Memory Cell Plates Using a Conductive Path
Packaged Semiconductor Components Having Substantially Rigid Support Members and Methods of Packaging Semiconductor Components
Disabling Electrical Connections Using Pass-Through 3D Interconnects and Associated Systems and Methods
Memory Devices for Detecting Known Initial States and Related Methods and Electronic Systems
Level Shifters, Memory Systems, and Level Shifting Methods
Apparatuses and Methods for Mixed Charge Pumps with Voltage Regulator Circuits
Patent:
9,722,489 →
Application:
15/144,682 →
Microelectronic Devices, Stacked Microelectronic Devices, and Methods for Manufacturing Such Devices
Program Inhibiting in Memory Devices
Patent:
9,666,282 →
Application:
15/145,204 →
Memory Access Techniques in Memory Devices with Multiple Partitions
Methods of Forming Memory Arrays
Novel Build-Up Package for Integrated Circuit Devices, and Methods of Making Same
Isolation Trench Fill Using Oxide Liner and Nitride Etch Back Technique with Dual Trench Depth Capability
Apparatuses and Methods Including Error Correction Code Organization
3D Nand Memory Z-Decoder
Patent:
9,679,650 →
Application:
15/148,408 →
Multiple Virtually Over-Provisioned, Virtual Storage Devices Created from a Single Physical Storage Device
Application:
15/149,021 →
Publication:
US 2016/0328179
Integrated Structures Having Gallium-Containing Regions
Textured Optoelectronic Devices and Associated Methods of Manufacture
Methods and Apparatuses Including an Active Area of a Tap Intersected by a Boundary of a Well
Memory Systems and Memory Programming Methods
Semiconductor Structures Including Rails of Dielectric Material
Boosting a Digit Line Voltage for a Write Operation
Patent:
9,721,638 →
Application:
15/151,065 →
Disposable Pillars for Contact Information
Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells
Signed Division in Memory
Apparatuses, Sense Circuits, and Methods for Compensating for a Wordline Voltage Increase
Methods of Forming Memory Devices with Isolation Structures
Forming Resistive Random Access Memories Together with Fuse Arrays
Magnetic Tunnel Junctions
Patent:
9,680,089 →
Application:
15/154,033 →
Semiconductor Device and Control Method of the Same
Three-Dimensional Devices Having Reduced Contact Length
Enhancing Nucleation in Phase-Change Memory Cells
Methods of Forming Memory Cells with Air Gaps and Other Low Dielectric Constant Materials
Integrated Circuitry Components, Switches, and Memory Cells
Assemblies Having Shield Lines of an Upper Wiring Level Electrically Coupled with Shield Lines of a Lower Wiring Level
Patent:
9,754,872 →
Application:
15/155,334 →
Array of Cross Point Memory Cells and Methods of Forming an Array of Cross Point Memory Cells
Semiconductor Structures Including Liners and Related Methods
Switched Interface Stacked-Die Memory Architecture
Apparatuses and Methods for Setting a Signal in Variable Resistance Memory
Systems and Methods for Memory System Management Based on Thermal Information of a Memory System
Methods of Forming a Non-Volatile Resistive Oxide Memory Cell and Methods of Forming a Non-Volatile Resistive Oxide Memory Array
Repair of Memory Devices Using Volatile and Non-Volatile Memory
Updating Reliability Data
Non-Deterministic Memory Protocol
Apparatuses and Methods for Shifting Data
Patent:
9,659,610 →
Application:
15/158,205 →
Semiconductor Device
Apparatuses and Methods for Performing Intra-Module Databus Inversion Operations
Array of Memory Cells and Methods of Forming an Array of Memory Cells
Power Reduction for a Sensing Operation of a Memory Cell
Patent:
9,715,918 →
Application:
15/161,952 →
Passing Access Line Structure in a Memory Device
Patent:
9,761,590 →
Application:
15/162,028 →
Magnetic Memory Cells, Semiconductor Devices, and Methods of Formation
Single Node Power Management for Multiple Memory Devices
Memory Read Apparatus and Methods
Memory Devices and Methods of Writing Memory Cells at Different Moments in Time
Memory Device Error Based Adaptive Refresh Rate Systems and Methods
Apparatus and Methods for Leakage Current Reduction in Integrated Circuits
Apparatus and Methods of Operating Memory for Exact and Inexact Searching of Feature Vectors
Pre-Compensation of Memory Threshold Voltage
Patent:
9,589,659 →
Application:
15/164,171 →
Interconnections for 3D Memory
Ferroelectric Devices and Methods of Forming Ferroelectric Devices
Application:
15/164,749 →
Publication:
US 2017/0345831
Leakage Current Detection
Electronic Device with Asymmetric Gate Strain
Methods and Devices for Reducing Array Size and Complexity in Automata Processors
Apparatus and Methods of Operating Memory with Erase De-Bias
Patent:
9,711,228 →
Application:
15/166,613 →
Interconnection for Memory Electrodes
Histogram Creation Process for Memory Devices
Semiconductor Devices and Structures and Methods of Formation
Semiconductor Devices Comprising Magnetic Memory Cells
Power Delivery Circuitry
Patent:
9,747,957 →
Application:
15/169,075 →
Memory Circuitry Comprising A Vertical String Of Memory Cells And A Conductive Via And Method Used In Forming A Vertical String Of Memory Cells And A Conductive Via
Logic Component Switch
Systems and Methods for Wafer Alignment
Patent:
9,748,128 →
Application:
15/170,517 →
Apparatuses and Methods for Performing Multiple Memory Operations
Apparatuses Including Memory Section Control Circuits with Global Drivers
Power Consumption Control
Apparatuses and Operation Methods Associated with Resistive Memory Cell Arrays with Separate Select Lines
Shifting Data
Charge Mirror-Based Sensing for Ferroelectric Memory
Apparatuses and Methods for Scalable Memory
Apparatuses and Methods for Selective Determination of Data Error Repair
Apparatuses and Methods for Forming Multiple Decks of Memory Cells
Integrated Structures Comprising Charge-Storage Regions Along Outer Portions of Vertically-Extending Channel Material
Patent:
9,748,265 →
Application:
15/176,072 →
Stack Access Control for Memory Device
Memory Cells and Methods of Forming Memory Cells
Memory Cells Comprising A Programmable Field Effect Transistor Having A Reversibly Programmable Gate Insulator
Apparatuses, Devices and Methods for Sensing a Snapback Event in a Circuit
Simulating Access Lines
Apparatuses and Methods Including Memory Access in Cross Point Memory
Magnetic Memory Cells, Semiconductor Devices, and Methods of Operation
Half Density Ferroelectric Memory and Operation
Semiconductor device assembly with through-mold cooling channel formed in encapsulant
Forming Self-Aligned Conductive Lines for Resistive Random Access Memories
Semiconductor Constructions and Methods of Forming Intersecting Lines of Material
Memory Protocol
Shared Error Detection and Correction Memory
Apparatuses with an Embedded Combination Logic Circuit for High Speed Operations
Patent:
9,762,247 →
Application:
15/184,077 →
Apparatuses and Methods for Data Transfer from Sensing Circuitry to a Controller
Plate Defect Mitigation Techniques
Resistance Variable Element Methods and Apparatuses
Solid State Transducer Devices, Including Devices Having Integrated Electrostatic Discharge Protection, and Associated Systems and Methods
Magnetic Memory Cell Structures, Arrays, and Semiconductor Devices
Integrated Structures and Methods of Forming Integrated Structures
Patent:
9,773,805 →
Application:
15/187,632 →
Memory Cell Imprint Avoidance
Patent:
9,721,639 →
Application:
15/188,886 →
Array Data Bit Inversion
Patent:
9,715,919 →
Application:
15/188,890 →
Programming Memories with Multi-Level Pass Signal
Bank to Bank Data Transfer
Connecting Memory Cells to a Data Line Sequentially While Applying a Program Voltage to the Memory Cells
Patent:
9,779,819 →
Application:
15/191,786 →
Semiconductor Device Structures
Methods of Forming Structures
Apparatuses and Methods for Erasure-Assisted Ecc Decoding
Memory Tile Access and Selection Patterns
Division Operations for Memory
Multi-Level Storage in Ferroelectric Memory
Managing Host Communication with a Regulator in a Low Power Mode
Methods of Forming Memory Cells, Arrays of Magnetic Memory Cells, and Semiconductor Devices
Error Correction Code (Ecc) Operations in Memory
Resistive Memory Cell Structures and Methods
Oscillator Controlled Random Sampling Method and Circuit
Apparatuses, Memories, and Methods for Address Decoding and Selecting an Access Line
Layout of Transmission Vias for Memory Device
Patent:
9,761,564 →
Application:
15/198,647 →
Cell Performance Recovery Using Cycling Techniques
Patent:
9,786,349 →
Application:
15/201,220 →
Power Management
Apparatuses and Methods for Providing Active and Inactive Clock Signals to a Command Path Circuit
Thermal Transfer Structures for Semiconductor Die Assemblies
Memory Device Including Multiple Select Gates and Different Bias Conditions
Patent:
9,728,266 →
Application:
15/205,574 →
Memory Device Including Current Generator Plate
Scan Chain Operation in Sensing Circuitry
Resistive Memory Having Confined Filament Formation
Apparatuses and Methods for Layer-by-Layer Error Correction
Methods and Systems for Using State Vector Data in a State Machine Engine
Dynamic Power-Down of a Block of a Pattern-Recognition Processor
Memory Cells Having a Folded Digit Line Architecture
Methods of Forming Transistor Gates
Elevationally-Extending String of Memory Cells Individually Comprising a Programmable Charge Storage Transistor and Method of Forming an Elevationally-Extending String of Memory Cells Individually Comprising a Programmable Charge Storage Transistor
Surface Modification Compositions, Methods of Modifying Silicon-Based Materials, and Methods of Forming High Aspect Ratio Structures
Patent:
9,653,307 →
Application:
15/210,249 →
Methods Of Forming An Elevationally Extending Conductor Laterally Between A Pair Of Conductive Lines
Patent:
9,754,946 →
Application:
15/210,511 →
Memory Structures and Arrays
Utilization of Data Stored in an Edge Section of an Array
Apparatuses and Methods for Transferring Data
Methods of Forming Silicon Nitride
Apparatuses and Methods for Write Address Tracking
Apparatuses and Methods Including Nested Mode Registers
Reduced Voltage Nonvolatile Flash Memory
Non-Volatile (Nv) Dual in-Line Memory Module (Dimm) Read and Write Operations
Application:
62/332,370 →
Apparatus and Methods for Shielding Devices from Radiated Emissions
Application:
62/349,939 →
Package-On-Package Semiconductor Device Assemblies Including One or More Windows and Related Methods and Packages
Application:
62/356,929 →
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 26, 2013
From: LI, HONGQI; DAMARLA, GOWRISANKAR; HANSON, ROBERT J.; LU, JIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031081/0717 →
Assignment of Assignor's Interest
Oct 22, 2014
From: PULUGURTHA, SRINIVAS; DHIR, SOURABH; GUPTA, RAJESH N; TANG, SANH D
To: MICRON TECHNOLOGY, INC.
Reel/Frame 034003/0719 →
Assignment of Assignor's Interest
Apr 19, 2016
From: HUSH, GLEN E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038322/0783 →
Assignment of Assignor's Interest
Apr 20, 2016
From: ZAWODNY, JASON T.; TIWARI, SANJAY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038335/0180 →
Assignment of Assignor's Interest
Apr 20, 2016
From: ZAWODNY, JASON T.; TIWARI, SANJAY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038334/0405 →
Assignment of Assignor's Interest
Apr 25, 2016
From: SHIBATA, TOMOYUKI; UEHARA, MINEHIKO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038520/0248 →
Assignment of Assignor's Interest
Apr 26, 2016
From: ISHIBASHI, SHUICHI; MIYANO, KAZUTAKA; FUJISAWA, HIROKI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038528/0083 →
Assignment of Assignor's Interest
May 2, 2016
From: GAJAPATHY, PARTHASARATHY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038437/0395 →
Supplement No. 1 to Patent Security Agreement
Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
Assignment of Assignor's Interest
Sep 21, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064987/0323 →