Oscillator controlled random sampling method and circuit

1. A method, comprising:

selecting a randomly-chosen seed row from among a stream of available data in a system;

performing a refresh operation to at least one selected row of memory in the memory system based on the randomly-chosen seed row;

selecting an oscillator having no synchronous relationship to periodic access cycles within a memory system; and

triggering an address sample after a row hammer repair (RHR) operation that is randomly-selected from activation row accesses within the memory system.

2. The method of claim 1 , further comprising determining a number of refresh cycles needed for RHR operations.

3. The method of claim 1 , further comprising allocating a predetermined fraction of refresh cycles to RHR operations.

4. The method of claim 1 , wherein the stream of available data includes row activation addresses for a row within the memory system.

5. The method of claim 4 , wherein a probability of selecting a particular row address from the stream of available is distributed approximately equally.

6. The method of claim 1 , further comprising:

after a toggle of the oscillator, sampling a subsequent activation address after the RHR operation;

overwriting the sampled subsequent activation address after a subsequent toggling of the oscillator;

continuing to overwrite a prior sampled activation address based on a state change of the oscillator occurring a random number of times;

discontinuing the overwrite operations; and

latching a most recently sampled activation address to provide the starting point for a RHR.

7. The method of claim 6 , further comprising:

making a determination of each address of a row of memory on either side of the latched activation address; and

based on the determination of each of the addresses of the rows of memory on either side of the most recently sampled activation address, performing a memory refresh operation to each of the rows of memory on either side of the most recently sampled activation address.

8. The method of claim 1 , wherein the refresh operation is performed without determining a number of times any of rows of memory are accessed.

9. The method of claim 1 , further comprising providing a seed address for a subsequent RHR operation.

10. The method of claim 1 , further comprising increasing a likelihood of selecting the randomly-chosen seed row from a row activation address within the stream of available data within a predetermined time interval, thereby lowering the possibility of selecting a row activation address from other time intervals.

11. The method of claim 10 , further comprising determining an average RHR tune interval based a time period of refresh cycles and a percentage of the refresh cycles that are to be dedicated to the RHR operations.

12. The method of claim 11 , further comprising selecting a number of the predetermined time intervals such that the number of the predetermined time intervals is greater than the average RHR time interval.

13. A method of operating a memory device, the method comprising:

obtaining an address of a random one of a plurality of rows in a memory device receiving an activation signal;

determining at least one row selected from a row before the obtained address and a row after obtained row address;

sending a refresh signal to the at least one row; and

discontinuing sampling of the plurality of rows in the memory device receiving an activation signal at a random time as determined by a cross of a preselected time interval and a random activate count latched when the sampling began.

14. The method of claim 13 , further comprising:

selecting a first randomly-chosen seed row within a first predetermined time interval; and

recording a value of the first randomly-chosen seed row.

15. The method of claim 14 , further comprising:

selecting a second randomly-chosen seed row within a second predetermined time interval;

overwriting the value of the first randomly-chosen seed row; and

recording a value of the second randomly-chosen seed row.