Switched interface stacked-die memory architecture
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
1. An apparatus, comprising:
a memory vault comprising a stacked plurality of memory arrays, each memory array of the stacked plurality of memory arrays located on a memory die of a plurality of stacked memory dies;
a memory vault controller (MVC) communicatively coupled to the memory vault; and
a memory vault repair logic (MVRL) component of the MVC, the MVRL to receive a memory request including a requested memory address, the MVRL including at least one lookup table to translate the requested memory address into a repair address, and the MVRL to send one or both of the memory request and the repair address to the memory vault.
2. The apparatus of claim 1 , wherein the MVC comprises a repair decode assessment module to estimate a latency associated with translating the requested memory address into the repair address.
3. The apparatus of claim 2 , wherein the MVC comprises a variable latency decision module (VLDM) coupled to the repair decode assessment module, the VLDM to cause the memory request including the requested memory address to be passed to a memory address decoder associated with a selected memory vault if the estimated latency is greater than a selected amount.
4. The apparatus of claim 1 , wherein the memory vault comprises a spare memory die.
5. The apparatus of claim 1 , wherein the MVC comprises a spare memory array.
6. The apparatus of claim 5 , wherein the spare memory array comprises one or both of a static random-access memory (SRAM) and a dynamic random-access memory (DRAM).
7. The apparatus of claim 1 , wherein the MVC is configured to provide memory sequencing operations.
8. The apparatus of claim 1 , wherein the MVC is configured to provide data buffering operations.
9. The apparatus of claim 1 , wherein the MVC is configured to provide memory array repair operations.
10. An apparatus, comprising:
a memory vault comprising a stacked plurality of memory arrays, each memory array of the stacked plurality of memory arrays located on a memory die of a plurality of stacked memory dies;
a memory vault controller (MVC) communicatively coupled to the memory vault; and
a memory vault repair logic (MVRL) component of the MVC, the MVRL to receive a memory request including a requested memory address and to send one or both the memory request and a modified memory request to the memory vault, the modified memory request to include a repair address, the MVRL comprising a partial address decoder to partially decode the requested memory address, a repair address lookup table communicatively coupled to the partial address decoder to translate the requested memory address into the repair address, and a bad block logic coupled to the partial address decoder to select the repair address lookup table from a plurality of repair address lookup tables.
11. The apparatus of claim 10 , wherein the plurality of repair address lookup tables comprises a direct-mapped table.
12. The apparatus of claim 10 , wherein the plurality of repair address lookup tables comprises a fully associative tag random-access memory.
13. The apparatus of claim 10 , wherein the plurality of repair address lookup tables comprises a set associative tag random-access memory.
14. The apparatus of claim 10 , wherein the MVRL comprises a repair decode assessment module coupled to the partial address decoder to estimate a latency associated with translating the requested memory address into the repair address.
15. The apparatus of claim 10 , wherein the MVRL comprises an arithmetic/logic unit (ALU) coupled to the repair address lookup table to calculate the repair address using an address offset stored in the repair address lookup table as an entry associated with the requested memory address.
16. An apparatus comprising:
a memory vault;
a memory vault controller (MVC) communicatively coupled to the memory vault; and
a memory vault repair logic (MVRL) component of the MVC, the MVRL to receive a memory request including a requested memory address, and the MVRL to send one or both of the memory request and a repair address to the memory vault, the MVC comprising:
a partial address decoder to partially decode the requested memory address;
a repair address lookup table communicatively coupled to the partial address decoder to translate the requested memory address into the repair address;
bad block logic coupled to the partial address decoder to select the repair address lookup table from a plurality of repair address lookup tables; and
a feedback loop operable to determine whether the requested memory address references a non-defective memory location.
17. The apparatus of claim 16 , wherein the bad block logic is configured to select the repair address lookup table based upon a number of bad blocks.
18. The apparatus of claim 16 , wherein the bad block logic is configured to select the repair address lookup table based upon a number of words in a bad block as determined by the partial address decoder.
19. The apparatus of claim 16 , wherein the MVRL further comprises an address bus gating logic coupled to pass the requested memory address to one or both of a memory address decoder and the partial address decoder.
20. The apparatus of claim 19 , wherein the memory address decoder comprises an address selector to reject a partially decoded requested memory address and to initiate decoding of the repair address if the requested memory address is determined to reference at least one defective memory cell.