Switched interface stacked-die memory architecture
View Patent ↗Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
1. A method comprising:
receiving a memory request including a requested memory address;
sending at least one of the memory request or a modified memory request to a selected vault, the modified memory request to include a repair address;
partially decoding the requested memory address;
estimating a latency associated with translating the requested memory address to the repair address to derive an estimated latency;
comparing the estimated latency to a threshold latency value; and
sending the memory request including the requested memory address to the selected vault if the estimated latency is greater than the threshold latency value.
2. The method of claim 1 , further comprising:
estimating a complexity of repair address generation; and
selecting a repair address lookup table from a plurality of repair address lookup tables based upon the complexity of repair address generation.
3. The method of claim 2 , wherein the plurality of repair address lookup tables comprises at least one of a direct-mapped table, a fully associative tag random-access memory (RAM), or a set associative tag RAM.
4. The method of claim 1 , further comprising:
selecting a repair address lookup table based upon at least one of a number of bad blocks or a number of words in a bad block.
5. The method of claim 1 , further comprising:
translating the requested memory address to the repair address.
6. The method of claim 1 , further comprising:
estimating a complexity of repair address generation;
selecting a repair address lookup table from a plurality of repair address lookup tables based upon the complexity of repair address generation; and
translating the requested memory address to the repair address.
7. The method of claim 1 , further comprising:
receiving at least one of the requested memory address or the repair address; and
decoding the requested memory address or the repair address into at least one of a memory die identifier, a memory bank identifier, a row address, or a column address.
8. The method of claim 1 , further comprising:
estimating a complexity of repair address generation;
selecting a repair address lookup table from a plurality of repair address lookup tables based upon the complexity of repair address generation;
translating the requested memory address to the repair address;
receiving at least one of the requested memory address or the repair address; and
decoding the requested memory address or the repair address into at least one of a memory die identifier, a memory bank identifier, a row address, or a column address.
9. The method of claim 1 , further comprising:
rejecting a partially decoded requested memory address if the requested memory address is determined to reference at least one defective memory cell; and
initiating decoding of the repair address.
10. The method of claim 1 , further comprising:
referencing a spare memory die component of the memory vault using the repair address.
11. The method of claim 10 , further comprising:
generating the repair address by substituting a die address associated with the spare memory die into the requested memory address.
12. The method of claim 1 , further comprising:
referencing at least one spare memory array fabricated on a logic die common with a memory vault repair logic module using the repair address.
13. A method comprising:
decoding a requested memory address;
estimating a latency associated with translating the requested memory address to a repair address to derive an estimated latency;
comparing the estimated latency to a threshold latency value; and
sending the requested memory address to a selected vault if the estimated latency is greater than the threshold latency value.
14. The method of claim 13 , further comprising:
estimating a complexity of repair address generation; and
selecting a repair address lookup table from a plurality of repair address lookup tables based upon the complexity of repair address generation.
15. The method of claim 13 , further comprising:
selecting a repair address lookup table based upon at least one of a number of bad blocks or a number of words in a bad block.
16. The method of claim 13 , wherein decoding the requested memory address includes decoding the requested memory address into at least one of a memory die identifier, a memory bank identifier, a row address, or a column address.
17. The method of claim 13 , further comprising:
rejecting the requested memory address if the requested memory address is determined to reference at least one defective memory cell; and
initiating decoding of the repair address.
18. The method of claim 13 , further comprising:
referencing a spare memory die component of the memory vault using the repair address.
19. The method of claim 13 , further comprising:
generating the repair address by substituting a die address associated with the spare memory die into the requested memory address.