IP Library Granted Patent US 10,446,571
Granted Patent B2
US 10,446,571 · App. 15/170,114 · Granted Oct 15, 2019

Memory circuitry comprising a vertical string of memory cells and a conductive via and method used in forming a vertical string of memory cells and a conductive via

Inventors: Hongbin Zhu (Boise, ID); Gurtej S. Sandhu (Boise, ID); Kunal R. Parekh (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L27/1052H01L27/1157H01L27/11521H01L27/11556H01L27/11568H01L27/11573
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Quick Facts
Patent No.
US 10,446,571
App. No.
15/170,114
Granted
Oct 15, 2019
Kind
B2
Abstract

A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Claims (43)

1. A method used in forming a vertical string of memory cells and a conductive via, comprising:

forming a first lower opening and a second lower opening into a lower material;

forming a first material within the first and second lower openings;

forming an upper material above the lower material and above the first material in the first and second lower openings;

forming a first upper opening through the upper material to the first material in the first lower opening;

removing at least a majority of the first material from the first lower opening through the first upper opening and forming channel material within the first lower and first upper openings for the vertical string of memory cells being formed;

after forming the channel material, forming a second upper opening through the upper material to the first material in the second lower opening;

forming conductive material of the conductive via within the second upper opening;

the first material being conductive; and

wherein forming the first material comprises:

forming a conductive container having opposing sidewalls and a base extending there-between in vertical cross-section in each of the first and second lower openings; and

forming conductive fill material within each conductive container in each of the first and second lower openings, the conductive fill material being of different composition from that of the opposing sidewalls and base of each conductive container in each of the first and second lower openings.

2. A method used in forming a vertical string of memory cells and a conductive via, comprising:

forming a first lower opening and a second lower opening into a lower material;

forming a first material within the first and second lower openings;

forming an upper material above the lower material and above the first material in the first and second lower openings;

forming a first upper opening through the upper material to the first material in the first lower opening;

removing at least a majority of the first material from the first lower opening through the first upper opening and forming channel material within the first lower and first upper openings for the vertical string of memory cells being formed;

after forming the channel material, forming a second upper opening through the upper material to the first material in the second lower opening;

forming conductive material of the conductive via within the second upper opening;

wherein the first material is conductive and said forming of the conductive material within the second upper opening comprises forming a container having opposing sidewalls and a base extending there-between in vertical cross-section in the second upper opening; and further comprising:

etching through the base of the container in the second upper opening to expose the first material in the second lower opening; and

forming conductor material in the second upper opening directly against the conductive first material of the opposing sidewalls of what was the former container in the second upper opening.

3. The method of claim 2 wherein the first material in the second lower opening comprises a conductive container having opposing sidewalls and a base extending there-between in the vertical cross-section in the second lower opening, the first material comprising conductive fill material within the conductive container in the second lower opening.

4. The method of claim 3 wherein the conductor material is of the same composition as the fill material and is formed directly against the fill material.

5. The method of claim 3 wherein the container and the first material within the second lower opening comprise two different composition materials with each having its own opposing sidewalls and a base extending between its sidewalls in the vertical cross-section.

6. The method of claim 5 wherein the etching to expose the first material in the second lower opening forms laterally opposing projections that project radially inward toward one another elevationally over tops of a radially-inner of the two different composition materials.

7. The method of claim 6 wherein the two laterally opposing projections are conductive.

8. The method of claim 6 wherein the two laterally opposing projections are insulative or semiconductive.

9. A method used in forming a vertical string of memory cells and a conductive via, comprising:

forming a first lower opening and a second lower opening through a lower material that is above a substrate, and forming the second lower opening deeper than the first lower opening;

forming a first material within the first and second lower openings;

forming an upper material above the lower material and above the first material in the first and second lower openings;

forming a first upper opening through the upper material to the first material in the first lower opening;

removing at least a majority of the first material from the first lower opening through the first upper opening and forming channel material within the first lower and first upper openings for the vertical string of memory cells being formed;

after forming the channel material, forming a second upper opening through the upper material to the first material in the second lower opening; and

forming conductive material of the conductive via within the second upper opening.

10. The method of claim 9 comprising forming the first material within the first and second lower openings in the same processing step.

11. The method of claim 9 comprising forming the second lower opening to have a wider maximum open dimension than the first lower opening.

12. The method of claim 9 ,

wherein the forming of each of the first lower opening and the second lower opening through the lower material comprises etching, the forming of the first lower opening and the second lower opening occurring in the same etching step;

wherein the second lower opening has a wider maximum open dimension than the first lower opening; and

using the wider maximum open dimension of the second lower opening compared to that of the first lower opening during said same etching step to inherently cause the second lower opening to be deeper than the first lower opening.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2016
From: ZHU, HONGBIN; SANDHU, GURTEJ S.; PAREKH, KUNAL R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 038762/0834 →
Continuity (1)
Related Publication 20170352677A1 · Dec 7, 2017
Cited By (1)
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