Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.
1. A memory system, comprising:
multiple data lines;
a common source;
an array of multiple resistance variable memory cells, each resistance variable memory cell coupled between one of the data lines and the common source, wherein each resistance variable memory cell comprises a resistance variable element and an access device; and
a memory controller configured to control,
provision of a standby data line voltage to the data lines;
performance of a program operation on the resistance variable element of a first resistance variable memory cell, comprising,
providing the access device of the first resistance variable memory cell with a first control gate voltage, and
providing a first data line voltage to a data line coupled to the first resistance variable memory cell; and
performance of an erase operation on the resistance variable element of a second resistance variable memory cell, comprising,
providing the access device of the second resistance variable memory cell with a second control gate voltage that is greater than the first control gate voltage, and
providing a second data line voltage that is different than the first data line voltage to a data line coupled to the second resistance variable memory cell.
2. The memory system of claim 1 , wherein the memory controller is configured maintain the common source at a common source voltage during both the performance of the program operation and the performance of the erase operation.
3. The memory system of claim 1 , wherein the memory controller is configured to selectively provide a common source voltage to the common source; and to selectively provide the standby data line voltage to the data lines which is equal to the common source voltage.
4. The memory system of claim 1 , wherein the access devices of the multiple resistance variable memory cells each comprise a field effect transistor (FET) having a gate.
5. The memory system of claim 4 , wherein the first and second control gate voltages are each applied to the gates of the FET of each of the first and second resistance variable memory cells, during respective programming and erase operations of the first and second resistance variable memory cells.
6. The memory system of claim 1 , wherein the access devices of the multiple resistance variable memory cells are electrically coupled between the resistance variable element of the respective resistance variable memory cell and a bit line associated with the respective resistance variable memory cell.
7. The memory system of claim 1 , wherein the access devices of the multiple resistance variable memory cells are electrically coupled between the resistance variable element of the respective resistance variable memory cell and the common source.
8. The memory system of claim 1 , wherein the second gate control voltage provided by the memory controller during an erase operation is greater than the first control gate voltage provided by the memory controller during a programming operation.
9. The memory system of claim 8 , wherein the second control gate voltage is substantially equal to the first control gate voltage plus the common source voltage.
10. The memory system of claim 1 , wherein the first data line voltage is less than the common source voltage.
11. The memory system of claim 1 , which is a memory device.