Semiconductor device and control method of the same
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.
1. A device comprising:
a first circuit configured to temporarily store information represented by a plurality of bits, each of the plurality of bits taking one of first and second levels;
a second circuit configured to detect a number of bits of the plurality of bits that each takes the first logic level;
a plurality of fuses provided correspondingly to the plurality of bits; and
a third circuit configured to blow up one or ones of the plurality of fuses corresponding to the bit or bits each taking the first logic level when the number of the bits each taking the first logic level is not larger than a number of bits of the plurality of bits that each takes the second logic level and to blow up one or more of the plurality of fuses corresponding to the bit or bits each taking the second logic level when the number of the bits each taking the first logic level is larger than the number of bits each taking the second logic level.
2. The device according to claim 1 , further comprising a memory device, wherein the information includes a defect address in the memory device to be relieved.
3. The device according to claim 1 , wherein the plurality of fuses includes an anti-fuse element.
4. A semiconductor device, comprising:
a bit determination circuit configured to count a number of bits at a first level in an input address formed of a plurality of bits;
a control circuit configured to store the input address to anon-volatile program element when the count number is smaller than a first number, wherein the control circuit is configured to store an inverted address obtained by inverting the input address to the non-volatile program element when the count number is equal or higher than the first number; and
a memory device, wherein the input address indicates a defect address in the memory device to be relieved.
5. The semiconductor device according to claim 4 , wherein the control circuit is configured to invert the input address to produce the inverted address when the count number is equal or larger than the first number and output the inverted address.
6. The semiconductor device according to claim 5 , wherein the program element comprises an anti-fuse element.
7. The semiconductor device according to claim 6 , wherein the control circuit configured to burn off the anti-fuse elements based on an address indicating the first level in the input address or the inverted address.
8. A semiconductor device, comprising:
a bit determination circuit configured to count a number of bits at a first level in an input address formed of a plurality of bits;
a control circuit configured to store the input address to a non-volatile program element when the count number is smaller than a first number, wherein the control circuit is configured to store an inverted address obtained by inverting the input address to the non-volatile program element when the count number is equal or higher than the first number; and
an internal power source to output a voltage for burning off the program element.
9. The semiconductor device according to claim 8 , further comprising a power supply control circuit to control the internal power source.
10. The semiconductor device according to claim 9 , wherein the power supply control circuit is configured to control the voltage of the internal power source according to the bit determination result signal.
11. A semiconductor device, comprising:
a bit determination circuit configured to count a number of bits at a first level in an input address formed of a plurality of bits;
a control circuit configured to store the input address to a non-volatile program element when the count number is smaller than a first number, wherein the control circuit is configured to store an inverted address obtained by inverting the input address to the non-volatile program element when the count number is equal or higher than the first number, and wherein the non-volatile program element comprises a program element of a TRUE-side polarity and a program element of a NOT-side polarity.
12. The semiconductor device according to claim 11 , wherein when the count number is equal to or higher than the first number, the control circuit supplies the inverted address to the program element of the NOT-side polarity.
13. The semiconductor device according to claim 11 , wherein when the count number is less than the first number, the control circuit supplies the input address signal to the program element of the TRUE-side polarity.
14. The semiconductor device of claim 4 , further comprising an address serial conversion circuit to convert signals supplied as parallel data and indicating the defective address to a serial signal, and to output the serial signal as the address signal.
15. A method of relieving a semiconductor device, comprising:
preparing a defect address indicating an address in a memory device to be relieved;
determining a number of bits at a first logic level in the defect address; and
programming the defect address to a program element when the number of bits is lower than a first number and an inverted defect address obtained by inverting the defect address to the program element when the number of bits is equal or larger than the first number.
16. The method of relieving the semiconductor device according to claim 15 , wherein the preparing includes,
writing data into the memory device;
reading the data and comparing the read data with an expected value, and
determining an address with the data written thereinto as the defect address when the read data and the expected value do not match each other.
17. The method of relieving the semiconductor device according to claim 16 , the preparing is performed responsive to a post repair package command.
18. The method of relieving the semiconductor device according to claim 17 , wherein the programming includes programming simultaneously the defect address or the inverted defect address to the program element.
19. The method of relieving the semiconductor device according to claim 18 , wherein the programming simultaneously includes programming simultaneously the program element corresponding to the bits at the first level in the defect address or the inverted defect address.