IP Library Granted Patent US 9,343,173
Granted Patent B2
US 9,343,173 · App. 14/469,352 · Granted May 17, 2016

Semiconductor device and control method of the same

Inventor: Susumu Takahashi (Tokyo, JP)
Assignee: Micron Technology, Inc.
G11C17/16G11C29/785G11C2029/4402
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Quick Facts
Patent No.
US 9,343,173
App. No.
14/469,352
Granted
May 17, 2016
Kind
B2
Abstract

A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.

Claims (42)

1. A semiconductor device, comprising:

a bit determination circuit to count a number of bits at a first level in an input address signal formed of a plurality of bits, and to output a result of counting indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal; and

a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal,

wherein the semiconductor device comprises:

an internal power source to output a voltage for cutting off program element; and

a power supply control circuit to control the internal power source, wherein the power supply control circuit to control the voltage of the internal power source according to the bit determination result signal.

2. The semiconductor device according to claim 1 , wherein the program element comprises an antifuse element.

3. The semiconductor device according to claim 1 , further comprising:

an address serial conversion circuit to convert signals supplied as parallel data and indicating a defective address to a serial signal, and to output the serial signal as the address signal.

4. The semiconductor device according to claim 1 , wherein

when the value of the count is equal to or higher than the predetermined determination threshold value, the selection control circuit cuts of the program element based on the address signal indicating a level other than the first level, and when the value of the count is less than the predetermined determination threshold value, the selection control circuit cuts off the program element based on the address signal indicating the first level.

5. The semiconductor device according to claim 1 , wherein

the program element comprises a program element of a TRUE-side polarity and a program element of a NOT-side polarity; and

when the value of the count is equal to or higher than the predetermined determination threshold value, the selection control circuit is to invert the first level of each bit of the address signal to a second level different from the first level and to invert the second level of each bit of the address signal to the first level, and to supply a signal obtained by the inversion to the program element of the NOT-side polarity, and when the value of the count is less than the predetermined determination threshold value, the selection control circuit does not invert the address signal, and is to supply the address signal to the program element of the TRUE-side polarity.

6. A semiconductor device, comprising:

a bit determination circuit to count a number of bits at a first level in an input address signal formed of a plurality of bits, and to output a result of counting indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal; and

a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal, wherein

the selection control circuit is to determine a priority order of the program element to be cut off, based on whether the value of the count is equal to or higher than the predetermined determination threshold value.

7. A semiconductor device, comprising:

a bit determination circuit to count a number of bits at a first level in an input address signal formed of a plurality of bits, and to output a result of counting indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal; and

a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal, wherein

the selection control circuit is to change the program element to be cut off and data on a defective address to be stored in the program element, according to whether or not the value of the count is equal to or higher than the predetermined determination threshold value.

8. The semiconductor device according to claim 1 , wherein

when the value of the count is equal to or higher than the predetermined determination threshold value, the selection control circuit is to invert each bit of the address signal, and to select the program element based on a serially converted address signal obtained by the inversion.

9. The semiconductor device according to claim 1 , wherein

the selection control circuit is to cut off the program element in time division, and according to a total number of the program element, to change a number of the program element to be cut off at each cut-off timing for the program element.

10. A method of relieving a semiconductor device, comprising:

writing data into a semiconductor memory device;

reading the mitten data, comparing the read data with an expected value, and determining an address with the data written thereinto as a defective address when the read data and the expected value do not match each other;

determining a bit by counting a number of bits at a first logic level in the defective address, the defective address being formed of a plurality of bits at one or both of the first logic level and a second logic level different from the first logic level, and outputting whether or not a value of the count exceeds a determination threshold value, as a bit determination result signal; and

controlling a selection to supply an address obtained by inverting the first and second logic levels of the respective bits of the defective address to a program element comprising an antifuse element based on the bit determination result signal.

11. The method of relieving the semiconductor device according to claim 10 , further comprising:

programming simultaneously the program element corresponding to the bits at the first level in the defective address supplied to the program element with the inversion, during the controlling the selection.

12. The method of relieving the semiconductor device according to claim 10 , wherein

during the controlling the selection, a priority order of the program element to be cut off is determined, based on whether or not the value of the count exceeds the determination threshold value.

13. The method of relieving the semiconductor device according to claim 10 , wherein

controlling the selection further changes a programming voltage to be supplied to the program element, based on whether or not the number of the count exceeds the determination threshold value.

14. The method of relieving the semiconductor device according to claim 10 , wherein

during the controlling the selection, the defective address is supplied to the program element in time division, and the program element is programmed according to a number of the bits in the time-divided defective address.

15. The method of relieving the semiconductor device according to claim 10 , wherein the controlling the selection is to supply the defective address without the inversion to the program element.

16. The method of relieving the semiconductor device according to claim 10 , further comprising:

programming simultaneously the program element corresponding to the bits at the first level in the defective address supplied to the program element without the inversion, during the controlling the selection.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2014
From: TAKAHASHI, SUSUMU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033631/0048 →
Priority Claims (1)
JP 2013-176507 · Aug 28, 2013 · national
Continuity (1)
Related Publication 20150063000A1 · Mar 5, 2015