IP Library Granted Patent US 9,899,073
Granted Patent B2
US 9,899,073 · App. 15/194,178 · Granted Feb 20, 2018

Multi-level storage in ferroelectric memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,899,073
App. No.
15/194,178
Granted
Feb 20, 2018
Kind
B2
Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

Claims (54)

1. A method of operating a ferroelectric memory cell, comprising:

receiving a first charge associated with a dielectric of the ferroelectric memory cell at a sense amplifier;

activating the sense amplifier at a first time;

receiving a second charge associated with a polarization of the ferroelectric memory cell at the sense amplifier; and

activating the sense amplifier at a second time after the first time.

2. The method of claim 1 , further comprising:

isolating the sense amplifier after receiving the first charge.

3. The method of claim 1 , further comprising:

activating a word line to at least in part initiate receiving the first charge at the sense amplifier.

4. The method of claim 1 , further comprising:

storing the first charge at a latch based at least in part on activating the sense amplifier at the first time.

5. The method of claim 4 , further comprising:

writing the first charge to the ferroelectric memory cell after activating the sense amplifier the second time.

6. The method of claim 4 , further comprising:

outputting information stored in the ferroelectric memory cell based at least in part on activating the sense amplifier the first time,

wherein outputting the information overlaps with receiving the second charge.

7. The method of claim 4 , further comprising:

writing the first charge to the ferroelectric memory cell before activating the sense amplifier the second time.

8. The method of claim 1 , wherein receiving the first charge occurs during a first period and receiving the second charge occurs during a second period, and wherein the first period overlaps with the second period.

9. The method of claim 1 , further comprising:

receiving a charge associated with a dielectric of a second ferroelectric memory cell at a second sense amplifier;

activating the second sense amplifier; and

outputting information stored in the second ferroelectric memory cell based at least in part on activating the second sense amplifier.

10. The method of claim 1 , further comprising:

deactivating a word line after activating the sense amplifier at the first time; and

precharging a target digit line using at least one equalizer.

11. The method of claim 1 , further comprising:

deactivating the sense amplifier;

deisolating the sense amplifier from a digit line; and

activating a word line to at least in part initiate receiving the second charge at the sense amplifier.

12. The method of claim 1 , wherein activating the sense amplifier after isolating the sense amplifier comprises:

increasing a voltage difference between digit lines within the sense amplifier.

13. The method of claim 1 , wherein the first charge has a first polarity and the second charge has a second polarity opposite of the first charge.

14. The method of claim 1 , wherein the first charge and the second charge have a same polarity.

15. The method of claim 1 , further comprising:

determining whether a voltage of a cell plate is less than or equal to a reference voltage of the sense amplifier when the sense amplifier is activated at the second time; and

writing the second charge to the ferroelectric memory cell after the second time based at least in part on the determination.

16. The method of claim 15 , further comprising:

writing the first charge to the ferroelectric memory cell after the second time.

17. The method of claim 1 , further comprising:

writing the first charge during a first period; and

writing the second charge during a second period that overlaps with the first period.

18. A method of operating a ferroelectric memory cell, comprising:

activating a word line a first time;

isolating a sense amplifier that is electronic communication with the word line after activating the word line;

activating the sense amplifier after isolating the sense amplifier;

capturing a dielectric charge from the sense amplifier; and

activating the word line a second time.

19. The method of claim 18 , further comprising:

activating the sense amplifier a second time after activating the word line the second time.

20. The method of claim 18 , further comprising:

deactivating the word line after the first time while the sense amplifier is isolated.

21. The method of claim 18 , further comprising:

determining a polarization charge after activating the word line the second time.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2016
From: KAWAMURA, CHRISTOPHER JOHN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039045/0750 →