IP Library Granted Patent US 9,711,565
Granted Patent B2
US 9,711,565 · App. 15/168,054 · Granted Jul 18, 2017

Semiconductor devices comprising magnetic memory cells

Inventors: Wayne I. Kinney (Emmett, ID); Witold Kula (Gilroy, CA); Stephen J. Kramer (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/222G11C11/161G11C11/1673G11C11/1675H01F10/3218H01L43/02H01L43/08H01L43/10H01F10/329H01L27/228
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Quick Facts
Patent No.
US 9,711,565
App. No.
15/168,054
Granted
Jul 18, 2017
Kind
B2
Abstract

Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication.

Claims (37)

1. A semiconductor device comprising at least one magnetic memory cell, the at least one magnetic memory cell comprising:

a magnetic cell core comprising:

magnetic regions, the magnetic regions comprising:

a free region exhibiting a switchable vertical magnetic orientation; and

a fixed region exhibiting a fixed vertical magnetic orientation,

at least one of the magnetic regions comprising an alternating structure of magnetic sub-regions and coupler sub-regions, the magnetic sub-regions each defining a height less than a height defined by each of the coupler sub-regions, neighboring magnetic sub-regions of the alternating structure exhibiting oppositely directed magnetic orientations; and

a non-magnetic region between the free region and the fixed region.

2. The semiconductor device of claim 1 , wherein the non-magnetic region is electrically insulative.

3. The semiconductor device of claim 1 , wherein each of the coupler sub-regions is directly between a pair of the magnetic sub-regions.

4. The semiconductor device of claim 1 , wherein the fixed region comprises the alternating structure of the magnetic sub-regions and the coupler sub-regions.

5. The semiconductor device of claim 4 , the magnetic regions further comprising another fixed region exhibiting a fixed vertical magnetic orientation and comprising the alternating structure of the magnetic sub-regions and the coupler sub-regions.

6. The semiconductor device of claim 5 , wherein the fixed region and the another fixed region are symmetrically disposed above and below, respectively, the free region.

7. The semiconductor device of claim 1 , wherein the free region does not comprise the alternating structure of the magnetic sub-regions and the coupler sub-regions.

8. The semiconductor device of claim 1 , wherein all of the magnetic regions of the magnetic cell core comprise the alternating structure of the magnetic sub-regions and the coupler sub-regions.

9. The semiconductor device of claim 1 , wherein the free region has a horizontal surface defining a smaller surface area than a surface area defined by a horizontal surface of the fixed region.

10. A semiconductor device, comprising:

an array of magnetic memory cells, at least one magnetic memory cell of the array comprising:

at least one magnetic region comprising an alternating structure of magnetic sub-regions and coupler sub-regions thicker than the magnetic sub-regions, magnetic material of the at least one magnetic region exhibiting a vertical magnetic orientation, neighboring magnetic sub-regions of the alternating structure being antiferromagnetically coupled with one another.

11. The semiconductor device of claim 10 , wherein each of the magnetic sub-regions consists of a monolayer of the magnetic material.

12. The semiconductor device of claim 10 , wherein:

one of the magnetic sub-regions is an uppermost sub-region of the alternating structure; and

another of the magnetic sub-regions is a lowermost sub-region of the alternating structure.

13. The semiconductor device of claim 10 , wherein the magnetic sub-regions of the alternating structure comprise:

magnetic sub-regions exhibiting a vertical magnetic orientation directed in a first vertical direction; and

magnetic sub-regions exhibiting a vertical magnetic orientation directed in a second vertical direction opposite the first vertical direction,

the magnetic sub-regions exhibiting the vertical magnetic orientation directed in the first vertical direction being thicker than the magnetic sub-regions exhibiting the vertical magnetic orientation directed in the second vertical direction.

14. The semiconductor device of claim 13 , wherein the at least one magnetic memory cell of the array further comprises a reference region exhibiting a vertical magnetic orientation in the second vertical direction.

15. The semiconductor device of claim 10 , wherein the magnetic sub-regions consist essentially of cobalt.

16. A semiconductor device, comprising:

an array of spin torque transfer magnetic random access memory (STT-MRAM) cells, at least one STT-MRAM cell thereof comprising:

a magnetic region exhibiting a fixed vertical magnetic orientation, the magnetic region comprising magnetic sub-regions interleaved with coupler sub-regions in an alternating structure, each of the coupler sub-regions having a greater height than a height of each of the magnetic sub-regions, neighboring magnetic sub-regions of the alternating structure exhibiting oppositely directed magnetic orientations;

another magnetic region exhibiting a switchable vertical magnetic orientation; and

an oxide region between the magnetic region and the another magnetic region,

a bit line and a word line in operable communication with the at least one STT-MRAM cell.

17. The semiconductor device of claim 16 , wherein the magnetic sub-regions comprise up to five monolayers of cobalt.

18. The semiconductor device of claim 16 , wherein the coupler sub-regions comprise at least one of ruthenium or rhodium.

19. The semiconductor device of claim 16 , wherein the magnetic region is free of palladium and platinum.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
Continuity (3)
Continuation 14728268 · Jun 2, 2015
Continuation 13527262 · Jun 19, 2012
Related Publication 20160276405A1 · Sep 22, 2016