Apparatuses and methods including error correction code organization
View Patent ↗Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
1. An apparatus comprising:
a controller to cause data to be stored in a first memory cell group of first memory cells of a memory device, to cause a first portion of an error correction code associated with the data to be stored in a second memory cell group of the first memory cells, the first memory cells located on a first level of the memory device;
the controller to cause additional data to be stored in a first memory cell group of second memory cells of the memory device and to cause a second portion of the error correction code to be stored in a second memory cell group of the second memory cells, the second memory cells located on a second level of the memory device; and
the controller to cause at least a portion of an error correction code associated with the additional data to be stored in a third memory cell group of the second memory cells concurrently with storing of the second portion of the error correction code in the second memory cell group of the second memory cells, the controller including;
an error correction code generator configured to generate the first and second portions of the error correction code, and the at least a portion of the error correction code associated with the additional data;
a write control unit coupled to the error correction code generator through a path and configured to transfer the data, the additional data, the first and second portions of the error correction code, and the error correction code associated with the additional data to the memory device; and
a storage unit including an input coupled to the path to receive the second portion of the error correction code and store the second portion of the error correction code when the first portion of the error correction code is transferred to the write control unit, the storage unit including an output coupled to the path to provide the second portion of the error correction code to the write control unit after the first portion of the error correction code is transferred to the write control unit.
2. The apparatus of claim 1 , wherein the controller is further configured to cause an additional portion of the error correction code associated with the data to be stored in a third memory cell group of the first memory cells.
3. The apparatus of claim 1 , wherein the data includes a page of information, and the error correction code is associated with the page of information.
4. The apparatus of claim 1 , wherein the memory device includes a first access line to access the first memory cells, and a second access line to access the memory device.
5. The apparatus of claim 4 , wherein the first access line is located immediately next to the second access line.
6. The apparatus of claim 1 , wherein the first and second memory cells are located on a semiconductor die, and the controller is located on another semiconductor die.
7. An apparatus comprising:
a controller to:
store first data in first memory cells of a memory device, the first memory cells associated with a first access line of the memory device;
store second data in a first memory cell group of second memory cells of the memory device, the second memory cells associated with a second access line of the memory device;
store at least a portion of an error correction code associated with the second data in a second memory cell group of the second memory cells; and
store a portion of an error correction code associated with the first data in a third memory cell group of the second memory cells, wherein the controller is configured to concurrently store the at least a portion of the error correction code associated with the second data and the portion of the error correction code associated with the first data, the controller including:
an error correction code generator configured to generate the portion of the error correction code associated with the first data, the at least a portion of the error correction code associated with the second data, and an additional portion of the error correction code associated with the second data;
a write control unit coupled to the error correction code generator through a path and configured to transfer the first data, the second data, the portion of the error correction code associated with the first data, the at least a portion of the error correction code associated with the second data, and the additional portion of the error correction code associated with the second data; and
a storage unit including an input coupled to the path to receive the at least a portion of the error correction code associated with the second data and store the at least a portion of the error correction code associated with the second data when the additional portion of the error correction code associated with the second data is transferred to the write control unit, the storage unit including an output coupled to the path to provide the at least a portion of the error correction code associated with the second data to the write control unit after the additional portion of the error correction code associated with the second data is transferred to the write control unit.
8. The apparatus of claim 7 , wherein the controller is further configured to store at least a portion of an error correction code associated with third data in the second memory cell group of the second memory cells.
9. The apparatus of claim 8 , wherein the controller is further configured to store an additional portion of the error correction code associated with the third data in the third memory cell group of the second memory cells.
10. The apparatus of claim 9 , wherein the portion of the error correction code associated with the first data is stored in the third memory cell group of the second memory cells before the additional portion of the error correction code associated with the third data is stored in the third memory cell group of the second memory cells.
11. The apparatus of claim 7 , wherein the at least a portion of the error correction code associated with the second data and the portion of the error correction code associated with the first data have difference sizes.
12. An apparatus comprising:
a controller to:
retrieve information from first memory cells of a memory device, the first memory cells associated with a first access line of the memory device;
generate data from the information using a first portion of error correction code associated with the data, the first portion of the error correction code associated with the data being included in the information;
retrieve a second portion of the error correction code associated with the data from second memory cells of the memory device if the data is unsuccessfully generated from the information using the first portion of the error correction code associated with the data, the second memory cells associated with a second access line of the memory device; and
generate data using the first portion of the error correction code associated with the data and the second portion of the error correction code associated with the data, wherein the controller is to cause at least a portion of an error correction code associated with additional data to be stored in the memory device concurrently with storing of the second portion of the error correction code in the memory device, the controller including:
an error correction code generator configured to generate the first and second portions of the error correction code, and the at least a portion of the error correction code associated with the additional data;
a write control unit coupled to the error correction code generator through a path and configured to transfer the data, the additional data, the first and second portions of the error correction code, and the error correction code associated with the additional data to the memory device; and
a storage unit including an input coupled to the path to receive the second portion of the error correction code and store the second portion of the error correction code when the first portion of the error correction code is transferred to the write control unit, the storage unit including an output coupled to the path to provide the second portion of the error correction code to the write control unit after the first portion of the error correction code is transferred to the write control unit.
13. The apparatus of claim 12 , wherein the first portion of the error correction code associated with the data and the second portion of the error correction code associated with the data have unequal sizes.
14. The apparatus of claim 12 , wherein the controller is configured to generate the first and second portions of the error correction code based on the data before the information is stored.
15. The apparatus of claim 14 , herein the controller is located on a memory controller separated from the memory device.
16. The apparatus of claim 12 , wherein the first and second memory cells and the controller are located on a same semiconductor die of the memory device.
17. The apparatus of claim 12 , wherein the first and second memory cells and the controller are located different semiconductor dice.