Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

1. A programming method, comprising:

applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of series-connected memory cells and to a second memory cell of a second string of series-connected memory cells while a data line is electrically connected to the first memory cell and electrically disconnected from the second memory cell; and

while continuing to apply the program voltage to the selected access line, electrically disconnecting the data line from the first memory cell and subsequently electrically connecting the data line to the second memory cell.

2. The method of claim 1 , wherein electrically disconnecting the data line from the first memory cell comprises deactivating a first select transistor connected to the data line and the first string of series-connected memory cells, and wherein electrically connecting the data line to the second memory cell comprises activating a second select transistor connected to the data line and the second string of series-connected memory cells.

3. The method of claim 1 , further comprising applying a pass voltage to respective ones of unselected access lines respectively commonly connected to respective ones of memory cells in the first string of series-connected memory cells other than the first memory cell and to respective ones of memory cells in the second string of series-connected memory cells other than the second memory cell while applying the program voltage to the selected access line while the data line is electrically connected to the first memory cell and while the data line is electrically disconnected from the second memory cell.

4. The method of claim 3 , further comprising continuing to apply the pass voltage to the respective ones of the unselected access lines respectively commonly connected to the respective ones of the memory cells in the first string of series-connected memory cells other than the first memory cell and to the respective ones of the memory cells in the second string of series-connected memory cells other than the second memory cell while electrically disconnecting the data line from the first memory cell and while subsequently electrically connecting the data line to the second memory cell.

5. The method of claim 1 , further comprising applying a same voltage to the data line while the data line is electrically connected to the first memory cell and while the data line is electrically connected to the second memory cell.

6. The method of claim 1 , further comprising applying a different voltage to the data line while the data line is electrically connected to the first memory cell than while the data line is electrically connected to the second memory cell.

7. The method of claim 1 , wherein applying the program voltage to the selected access line while the data line is electrically connected to the first memory cell programs first data in the first memory cell and electrically connecting the data line to the second memory cell while continuing to apply the program voltage to the selected access line programs second data in the second memory cell, and further comprising programming the first and second data in a single memory cell connected to a different access line than the selected access line.

8. The method of claim 7 , further comprising reading the first data from the first memory cell and the second data from the second memory cell before programming the first and second data in the single memory cell.

9. The method of claim 8 , further comprising verifying that the first data is programmed in the first memory cell before reading the first data from the first memory cell and verifying that the second data is programmed in the second memory cell before reading the second data from the second memory cell.

10. The method of claim 8 , further comprising:

storing the first data in a first page buffer connected to the data line before programming the first data in the first memory cell and storing the second data in a second page buffer connected to the data line before programming the second data in the second memory cell; and

storing the first data read from first memory cell in the first page buffer and storing the second data read from the second memory cell in the second page buffer;

wherein programming the first and second data in the single memory cell comprises programming the first data stored in the first page buffer and the second data stored in the second page buffer in the single memory cell; and

wherein programming the first and second data in the single memory cell comprises electrically connecting the data line to the single memory cell.

11. The method of claim 7 , wherein the first data comprises a plurality of bits of data and the second data comprises a plurality of bits of data.

12. The method of claim 1 , further comprising:

electrically disconnecting the data line from the second memory cell and removing the program voltage from the selected access line;

applying a sensing voltage to the selected access line;

electrically connecting the first memory cell to the data line while applying the sensing voltage to the selected access line and while the second memory cell is electrically disconnected from the data line; and

while continuing to apply the sensing voltage to the selected access line electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line.

13. The method of claim 12 , wherein the sensing voltage comprises a voltage selected from the group consisting of a read voltage and a program-verify voltage.

14. The method of claim 1 , wherein applying the program voltage to the selected access line while the data line is electrically connected to the first memory cell is to program a plurality of bits of data in the first memory cell, wherein respective ones of the plurality of bits of data are respectively stored in respective ones of a plurality of page buffers connected to the data line, and further comprising:

electrically disconnecting the data line from the second memory cell and removing the program voltage from the selected access line;

electrically connecting the first memory cell to the data line;

applying a plurality of increasing program-verify voltages to the selected access line while the first memory cell is electrically connected to the data line and while the second memory cell is electrically disconnected from the data line;

storing data in a data register connected to the data line in response to one of the plurality of increasing program-verify voltages;

comparing the data stored in the data register to the plurality of bits that are respectively stored in the respective ones of the plurality of page buffers; and

determining whether the first memory cell is programmed to the plurality of bits of data in response to comparing the data stored in the data register to the plurality of bits that are respectively stored in the respective ones of the plurality of page buffers.

15. The method of claim 14 , further comprising determining that the first memory cell is programmed to the plurality of bits of data in response to the data stored in the data register matching the plurality of bits that are respectively stored in the respective ones of the plurality of page buffers.

16. The method of claim 14 , wherein the plurality of bits of data are a plurality of first bits of data and the plurality of page buffers are a plurality of first page buffers, wherein electrically connecting the data line to the second memory cell while continuing to apply the program voltage to the selected access line is to program a plurality of second bits of data in the second memory cell, wherein respective ones of the plurality of second bits of data are respectively stored in respective ones of a plurality of second page buffers connected to the data line, wherein the plurality of increasing program-verify voltages are a plurality of first increasing program-verify voltages of a sensing voltage applied to the selected access line, and further comprising:

electrically disconnecting the first memory cell from the data line;

decreasing the sensing voltage from a greatest one of the plurality of first increasing program-verify voltages of the sensing voltage applied to the selected access line to a lowest one of a plurality of second increasing program-verify voltages of the sensing voltage applied to the selected access line;

electrically connecting the second memory cell to the data line;

applying the plurality of second increasing program-verify voltages to the selected access line, starting with the lowest one of the plurality of second increasing program-verify voltages, while the second memory cell is electrically connected to the data line;

storing data in the data register connected to the data line in response to one of the plurality of second increasing program-verify voltages;

comparing the data that was stored in the data register in response to the one of the plurality of second increasing program-verify voltages to the plurality of second bits of data that are respectively stored in the respective ones of the plurality of second page buffers; and

determining whether the second memory cell is programmed to the plurality of second bits of data in response to comparing the data that was stored in the data register in response to the one of the plurality of second increasing program-verify voltages to the plurality of second bits that are respectively stored in the respective ones of the plurality of second page buffers.

17. A memory device, comprising:

a controller;

wherein the controller is configured to cause the memory device to apply a program voltage to a selected access line commonly connected to a first memory cell of a first string of series-connected memory cells and to a second memory cell of a second string of series-connected memory cells while a data line is electrically connected to the first memory cell and while the data line is electrically disconnected from the second memory cell; and

wherein the controller is configured to cause the memory device, while the memory device continues to apply the program voltage to the selected access line, to electrically disconnect the data line from the first memory cell and subsequently electrically connect the data line to the second memory cell.

18. The memory device of claim 17 , wherein the controller being configured to cause the memory device to apply the program voltage to the selected access line while the data line is electrically connected to the first memory cell causes the memory device to program first data in the first memory cell and wherein the controller being configured to cause the memory device, while the memory device continues to apply the program voltage to the selected access line, to electrically connect the data line to the second memory cell causes the memory device to program second data in the second memory cell, and wherein the controller is configured to cause the memory device to program the first and second data in a single memory cell connected to a different access line than the selected access line.

19. The memory device of claim 18 , wherein the controller is configured to cause the memory device to read the first data from the first memory cell and the second data from the second memory cell before causing the memory device to program the first and second data in the single memory cell connected to the different access line than the selected access line.

20. The memory device of claim 18 , wherein the first data comprises a plurality of bits of data and the second data comprises a plurality of bits of data.