Semiconductor device assembly with through-mold cooling channel formed in encapsulant
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
1. A semiconductor device assembly comprising:
a first semiconductor die having a base region and a peripheral region adjacent to the base region;
at least one second semiconductor die at the base region; and
a thermal transfer device attached to the first and second semiconductor dies, the thermal transfer device including an encapsulant at least partially surrounding the second semiconductor die, a via formed in the encapsulant that at least partially defines a cavity adjacent to the peripheral region of the first semiconductor die, and a working fluid at least partially filling the cavity,
wherein the peripheral region of the first semiconductor die includes an active surface, and wherein the active surface is in direct contact with the working fluid.
2. The semiconductor device assembly of claim 1 wherein:
the encapsulant includes an upper surface;
the cavity includes an opening formed in the upper surface; and
the thermal transfer device further includes a heat dissipator attached to the upper surface and covering the opening of the cavity.
3. The semiconductor device assembly of claim 1 wherein:
the encapsulant includes an upper surface;
the cavity includes an opening formed in the upper surface; and
the thermal transfer device further includes a condenser structure attached to the upper surface and in fluid communication with the cavity via the opening.
4. The semiconductor device assembly of claim 3 wherein:
the condenser structure includes an outer wall;
the outer wall defines an internal compartment; and
the working fluid at least partially fills the compartment.
5. The semiconductor device assembly of claim 1 wherein the second semiconductor die has an outer perimeter, and wherein the encapsulant includes a sidewall portion between the outer perimeter and the cavity.
6. The semiconductor device assembly of claim 5 wherein the cavity is a channel surrounding the outer perimeter of the second semiconductor die.
7. The semiconductor device assembly of claim 1 wherein:
the cavity is a first hole;
the encapsulant at least partially defines a second hole that is proximate the first hole; and
the working fluid at least partially fills the second hole.
8. The semiconductor device assembly of claim 1 wherein:
the second semiconductor die includes a first side and a second side opposite the first side;
the cavity is a first trench that extends over the first side of the second semiconductor die;
the encapsulant at least partially defines a second trench that extends over the second side of the second semiconductor die; and
the working fluid at least partially fills the second trench.
9. The semiconductor device assembly of claim 1 wherein:
the cavity is a first cavity;
the encapsulant includes an upper region above the second semiconductor die;
the encapsulant defines a second cavity in the upper region; and
the working fluid at least partially fills the second cavity.
10. A semiconductor device assembly:
a first semiconductor die having a base region and a peripheral region adjacent to the base region;
at least one second semiconductor die at the base region; and
a thermal transfer device attached to the first and second semiconductor dies, the thermal transfer device including an encapsulant at least partially surrounding the second semiconductor die, a via formed in the encapsulant that at least partially defines a cavity adjacent to the peripheral region of the first semiconductor die, and a working fluid at least partially filling the cavity,
wherein the peripheral region of the first semiconductor die includes a thermally conductive feature, and wherein the thermally conductive feature is in direct contact with the working fluid.
11. The semiconductor device assembly of claim 10 wherein the thermally conductive feature is an interface material between the peripheral region of the first semiconductor die and the working fluid.
12. A semiconductor device assembly, comprising:
a plurality of semiconductor dies including a first die and a stack of second dies on the first die;
an encapsulant at least partially encapsulating the plurality of semiconductor dies, wherein the encapsulant includes first and second sidewalls defining a cavity, wherein the encapsulant further includes an upper surface, and wherein the cavity extends past the stack of second dies between a peripheral region of the first die and the upper surface of the encapsulant;
a thermal conductor at least partially filling the cavity, wherein the thermal conductor includes a solid fill material; and
a heat dissipator attached to the upper surface.
13. The semiconductor device assembly of claim 12 wherein:
the cavity is a first cavity;
the encapsulant further includes third and fourth sidewalls defining a second cavity over a region of the stack of second dies; and
the peripheral region of the first die is peripheral to the region of the stack of second dies.
14. The semiconductor device assembly of claim 13 wherein the solid fill material at least partially fills the first and second cavities.
15. The semiconductor device assembly of claim 12 wherein the solid fill material thermally couples the peripheral region of the first die to the heat dissipator.
16. The semiconductor device assembly of claim 15 wherein the solid fill material is soldered to at least one of the heat dissipator and the peripheral region of the first die.
17. The semiconductor device assembly of claim 12 wherein the second dies are memory dies.
18. The semiconductor device assembly of claim 17 wherein the first die is a logic die.