Methods and apparatuses including an active area of a tap intersected by a boundary of a well
View Patent ↗Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.
1. An apparatus comprising:
a memory array comprising a plurality of memory cells; and
support circuitry coupled to the memory array, the support circuitry comprising a semiconductor device comprising a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity;
a tap to the well comprising an active area having a lightly doped area outside a boundary of the well and a more heavily doped area outside a boundary of the semiconductor structure.
2. The apparatus of claim 1 , wherein the memory array and the support circuitry are included in a memory device.
3. The apparatus of claim 2 , further comprising a processor coupled to the memory device.
4. The apparatus of claim 1 , wherein the semiconductor structure comprises a P-well, the well comprises an N-well, the more heavily doped area comprises an N+ area, and the lightly doped area comprises an N− area.
5. The apparatus of claim 4 , wherein the semiconductor structure comprises a N-well, the well comprises an P-well, the more heavily doped area comprises a P+ area, and the lightly doped area comprises a P− area.
6. The apparatus of claim 1 , comprising a contact over the more heavily doped area.
7. The apparatus of claim 6 , wherein the active area is over a substantially vertical junction between the lightly doped area and the more heavily doped area, and
wherein the contact is entirely over the more heavily doped area.
8. The apparatus of claim 1 , wherein the more heavily doped area is limited to under the contact.
9. The apparatus of claim 1 , wherein the well creates an electric field peak at the edge of the well within lightly doped area of the active area to increase breakdown voltage of the apparatus.
10. The apparatus of claim 1 , comprising an isolation area, wherein the lightly doped area is between the contact and the isolation area.
11. The apparatus of claim 1 , wherein the active area is over a junction between the lightly doped area and the more heavily doped area.
12. The apparatus of claim 11 , wherein the junction comprises a substantially vertical junction.
13. The apparatus of claim 11 , wherein the junction comprises a substantially vertical junction, and
wherein the contact is entirely over the more heavily doped area.
14. The apparatus of claim 11 , wherein the contact is entirely over the more heavily doped area.
15. The apparatus of claim 11 , wherein the contact is not over the lightly doped area.
16. An apparatus comprising:
a memory array comprising a plurality of memory cells;
support circuitry coupled to the memory array, the support circuitry comprising a semiconductor device comprising a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity;
a tap to the well comprising an active area having a lightly doped area outside a boundary of the well and a more heavily doped area outside a boundary of the semiconductor structure; and
a contact over the more heavily doped area.
17. The apparatus of claim 16 , wherein the contact is not over the lightly doped area.
18. The apparatus of claim 16 , wherein the contact is entirely over the more heavily doped area.
19. The apparatus of claim 16 , wherein the active area is over a junction between the lightly doped area and the more heavily doped area.
20. The apparatus of claim 16 , wherein the junction comprises a substantially vertical junction.