Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor
View Patent ↗Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.
1. An apparatus comprising:
a plurality of semiconductor pillars situated in a grid, the grid of pillars including rows and columns of pillars;
a plurality of select gate drain connections situated around the pillars;
a plurality of semiconductor control gate connections situated around the pillars below the select gate drain connections,
a plurality of first select gate source connections situated around the pillars below the control gate connection;
a plurality of second select gate source connections situated around the pillars below the first select gate source connections; and
a drive transistor having a drain coupled to both:
the plurality of select gate drain connections; and
the plurality of first select gate source connections or the plurality of second select gate source connections.
2. The apparatus of claim 1 , further comprising:
a plurality of semiconductor data lines, each data line of the data lines connected to a first end of each pillar in a column of pillars of the columns of pillars.
3. The apparatus of claim 2 , further comprising:
a source connected to each of the semiconductor pillars at a second end of the semiconductor pillars, the second end opposite the first end.
4. The apparatus of claim 1 , wherein each select gate drain connection of the select gate drain connections is around each pillar in a row of pillars of the rows of pillars.
5. The apparatus of claim 1 , further comprising a dielectric material between each of the select gate drain connections and the pillar.
6. The apparatus of claim 1 , wherein each control gate connection of the control gate connections is around each pillar in the grid of pillars.
7. The apparatus of claim 1 , further comprising a semiconductor material between each of the control gate connections and each of the pillars, the semiconductor material separated from each of the pillars by a first dielectric material.
8. The apparatus of claim 7 , wherein the semiconductor material is separated from each of the control gate connections by a second dielectric material.
9. The apparatus of claim 1 , wherein the drive transistor is coupled to both the plurality of select gate drain connections and the plurality of first select gate source connections.
10. The apparatus of claim 1 , wherein the drive transistor is coupled to both the plurality of select gate drain connections and the plurality of second select gate source connections.
11. An apparatus comprising:
a plurality of U-shaped semiconductor pillars situated in a grid, the grid of pillars including rows and columns of pillars, each pillar of the U-shaped pillars including a first leg and a second leg with second legs of directly adjacent pillars next to each other;
a plurality of select gate drain connections situated around the first legs of the pillars;
a plurality of first semiconductor control gate connections situated around the first legs of the pillars below the select gate drain connections;
a plurality of first select gate source connections situated around the second legs of the pillars;
a plurality of second select gate source connections situated around the second legs of the pillars below the first select gate source connections;
a plurality of second semiconductor control gate connections situated around the second legs of the pillars below the second select gate source connections; and
a drive transistor having a drain coupled to both:
the plurality of select gate drain connections; and
the plurality of first select gate source connections or the plurality of second select gate source connections.
12. The apparatus of claim 11 , further comprising:
a plurality of semiconductor data lines, each data line of the data lines connected to a first end of each first leg of each pillar above the plurality of select gate drain connections.
13. The apparatus of claim 12 , further comprising:
a source connected to a first end of each second leg of each of the semiconductor pillars, the source connected to the second legs above the plurality of first select gate source connections.
14. The apparatus of claim 11 , wherein each select gate drain connection of the select gate drain connections is around each pillar in a row of pillars of the grid of pillars.
15. The apparatus of claim 11 , further comprising a dielectric material between each of the select gate drain connections and the pillar.
16. The apparatus of claim 11 , wherein each control gate connection of the control gate connections is around each pillar in a row of pillars in the grid of pillars.
17. The apparatus of claim 11 , further comprising a semiconductor material between each of the control gate connections and each of the pillars, the semiconductor material separated from each of the pillars by a first dielectric material.
18. The apparatus of claim 17 , wherein the semiconductor material is separated from each of the control gate connections by a second dielectric material.
19. The apparatus of claim 11 , wherein the drive transistor is coupled to both the plurality of select gate drain connections and the plurality of first select gate source connections.
20. The apparatus of claim 11 , wherein the drive transistor is coupled to both the plurality of select gate drain connections and the plurality of second select gate source connections.