Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.
1. An array of resistive memory cells, comprising:
a first resistive memory cell in a first region of the array and comprising:
a first conductive plug and a second conductive plug separated by a first dielectric material and formed on a substrate;
a first heater material formed only on the first conductive plug and portions of the first dielectric material;
a first resistance variable material formed on the first heater material; and
a first conductive cap material formed on the first resistance variable material; and
a second resistive memory cell in a second region of the array and comprising:
a third conductive plug and a fourth conductive plug separated by said first dielectric material and formed on the substrate;
a second heater material formed only on the third conductive plug and portions of the first dielectric material;
a second resistance variable material formed on the second heater material, wherein the second resistance variable material is different than the first resistance variable material; and
a second conductive cap material formed on the second resistance variable material.
2. The array of claim 1 , wherein the first resistance variable material has a first electrothermal property and the second resistance variable material has a second electrothermal property that is different from the first electrothermal property.
3. The array of claim 1 , wherein the second resistance variable material comprises an ion concentration different from an ion concentration of the first resistance variable material.
4. The array of claim 1 , wherein first and second resistance variable materials include phase change materials.
5. The array of claim 1 , wherein the first and second resistive memory cells each include a self-aligned structure comprising the respective first and second resistance variable materials formed between respective first and second conductive elements.
6. The array of claim 5 , wherein the first conductive element is the first heater material and the first and second resistance variable materials are phase change materials.
7. The array of claim 1 , wherein the first resistive memory cell belongs to a first sub-array and the second resistive memory cell belongs to a second sub-array.
8. The array of claim 1 , wherein a first region of the array including the first resistance variable material is configured to store a first type of data, and a second region of the array including the second resistance variable material is configured to store a second type of data.
9. The array of claim 8 , wherein the first region of the array has a higher associated retention capability than the second region of the array.
10. The array of claim 8 , wherein the first region of the array has a higher associated programming throughput than the second region of the array.
11. The array of claim 1 , wherein:
the first resistive memory cell provides higher speed and longer endurance as compared to the second resistive memory cell; and
the second resistive memory cell provides higher temperature retention capability as compared to the first resistive memory cell.