Cell performance recovery using cycling techniques
View Patent ↗Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.
1. A method of operating a memory array, comprising:
performing a plurality of access operations on a ferroelectric memory cell;
calculating a duration corresponding to fatigue of the ferroelectric memory cell using a first delay between access operations of the plurality of access operations and a number of access operations in the plurality of access operations;
identifying a fatigue state of the ferroelectric memory cell based at least in part on the calculated duration; and
applying a plurality of pulses to the ferroelectric memory cell based at least in part on identifying the fatigue state, wherein a second delay between pulses of the plurality of pulses is less than the first delay.
2. The method of claim 1 , wherein the first delay comprises an average duration between access operations for the ferroelectric memory cell, and wherein the second delay comprises a duration between pulses of the plurality of pulses.
3. The method of claim 1 , wherein the plurality of pulses is applied after determining the number of access operations has been performed on the ferroelectric memory cell.
4. The method of claim 3 , wherein a number of pulses included in the plurality of pulses is based at least in part on the number of access operations performed on the ferroelectric memory cell.
5. The method of claim 1 , wherein applying the plurality of pulses comprises applying voltages of alternating polarity across a ferroelectric capacitor of the ferroelectric memory cell with each pulse of the plurality of pulses.
6. The method of claim 5 , wherein a third delay comprises a first duration between a first pulse associated with a first polarity and a second pulse associated with a second polarity, and wherein a fourth delay comprises a second duration between the second pulse associated with the second polarity and a third pulse associated with the first polarity.
7. The method of claim 6 , wherein the first duration and the second duration are of different durations.
8. The method of claim 1 , wherein a magnitude of a voltage of each pulse of the plurality of pulses is greater than a magnitude of a voltage used for each access operation of the plurality of access operations.
9. The method of claim 1 , the method further comprising:
storing a logic state of the ferroelectric memory cell in an additional memory cell before applying the plurality of pulses.
10. The method of claim 1 , further comprising:
performing additional access operations on the ferroelectric memory cell after applying the plurality of pulses.
11. A method of operating a memory array, comprising:
performing a plurality of access operations on a ferroelectric memory cell of the memory array;
calculating a duration corresponding to fatigue of the ferroelectric memory cell using a first delay between access operations of the plurality of access operations and a number of access operations in the plurality of access operations;
identifying a fatigue state for the ferroelectric memory cell based at least in part on the calculated duration; and
performing a recovery operation of a polarization factor of the ferroelectric memory cell, wherein the recovery operation comprises applying a plurality of pulses to the ferroelectric memory cell.
12. The method of claim 11 , further comprising:
monitoring a number of performed access operations on the ferroelectric memory cell; and
identifying the fatigue state based at least in part on the number of performed access operations.
13. The method of claim 11 , wherein the first delay is based at least in part on an average duration between access operations, the method further comprising:
determining the average duration based at least in part on a use of the ferroelectric memory cell.
14. The method of claim 13 , wherein the recovery operation is performed based on an event selected from a group consisting of:
receiving an input from a user triggering the recovery operation;
receiving a periodic signal triggering the recovery operation;
determining that an access operation is scheduled for a section of the memory array including the ferroelectric memory cell;
identifying the section of the memory array has been accessed a number of times greater than a threshold value;
identifying that an external power supply is available to power the memory array; and
detecting a number of access-based errors exceeds a threshold value.
15. The method of claim 11 , further comprising:
identifying the number of access operations corresponding to the fatigue state based at least in part on a model of the ferroelectric memory cell.
16. An electronic memory apparatus, comprising:
a ferroelectric memory cell; and
a controller in electronic communication with the ferroelectric memory cell, wherein the controller is operable to:
perform a plurality of access operations on the ferroelectric memory cell;
calculate a duration corresponding to fatigue of the ferroelectric memory cell using a first delay between access operations of the plurality of access operations and a number of access operations in the plurality of access operations;
identify a fatigue state of the ferroelectric memory cell based at least in part on the calculated duration; and
apply a plurality of pulses to the ferroelectric memory cell based at least in part on the fatigue state of the ferroelectric memory cell.
17. The electronic memory apparatus of claim 16 , wherein the controller is further operable to:
apply the plurality of pulses based on an event selected from a group consisting of:
receiving an input from a user triggering a recovery operation;
receiving a periodic signal triggering a recovery operation;
determining that an access operation is scheduled for a section of a memory array including the ferroelectric memory cell;
identifying a section of a memory array including the ferroelectric memory cell has been accessed a number of times greater than a threshold value;
identifying that an external power supply is available to power a memory array including the ferroelectric memory cell; and
detecting a number of access-based errors exceeds a threshold value.
18. The electronic memory apparatus of claim 16 , wherein the controller is further operable to:
apply voltages of alternating polarity across a ferroelectric capacitor of the ferroelectric memory cell with each pulse of the plurality of pulses.