Forming resistive random access memories together with fuse arrays
View Patent ↗A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
1. An apparatus, comprising:
an array of resistive memory elements formed on a substrate, wherein the array includes first and second sets of parallel trenches, and wherein the second set of parallel trenches is orthogonal to the first set of parallel trenches; and
a fuse array formed on the substrate, wherein the fuse array includes a third set of parallel trenches and a continuous wordline configured to drive one or more cells of the fuse array.
2. The apparatus of claim 1 , wherein the first set of parallel trenches is shallower than the second set of parallel trenches.
3. The apparatus of claim 1 , wherein the one or more cells of the fuse array are programmable by a reverse bias current.
4. The apparatus of claim 3 , wherein the reverse bias current causes destructive failure of the one or more cells in the fuse array.
5. The apparatus of claim 1 , wherein the third set of trenches define a plurality of address lines of the fuse array; and
each cell of the one or more cells of the fuse array corresponds to an address line of the plurality of address lines.
6. The apparatus of claim 1 , wherein each cell of the one or more cells of the fuse array comprises a singulated heater.
7. The apparatus of claim 1 , wherein the array of resistive memory elements and the fuse array are formed on a common die.
8. An apparatus comprising:
a chalcogenide memory array formed on a substrate and having a first set of trenches and a second set of trenches orthogonal to the first set of trenches;
a fuse array formed on the substrate and having continuous wordlines configured to drive one or more cells of the fuse array.
9. The apparatus of claim 8 , wherein the first set of trenches are deeper than the second set of trenches.
10. The apparatus of claim 8 , wherein the one or more cells of the fuse array each comprise a fuse contact.
11. The apparatus of claim 8 , wherein the continuous wordlines are configured to reduce parasitic resistance in the fuse array.
12. The apparatus of claim 8 , wherein the fuse array is programmable by applying a reverse biased current to the one or more cells of the fuse array.
13. The apparatus of claim 8 , wherein the fuse array further comprises a third set of trenches defining the continuous wordlines.
14. The apparatus of claim 13 , wherein the third set of trenches are extensions of the first set of trenches.
15. A method comprising:
forming a first set of trenches having a first depth;
forming a second set of trenches having a second depth, wherein the second set of trenches is perpendicular to the first set of trenches to define an array of resistive memory elements; and
forming a third set of trenches having the first depth to define a fuse array having continuous wordlines configured to drive one or more cells of the fuse array.
16. The method of claim 15 , wherein each cell in the fuse array comprises a collector, the continuous wordline, a fuse contact, and a cap over the fuse contact.
17. The method of claim 16 , further comprising:
forming a heater over at least a portion of the cap for each cell in the fuse array.
18. The method of claim 17 , wherein the heater is L-shaped.
19. The method of claim 18 , further comprising:
forming a chalcogenide layer over the heater.
20. The method of claim 19 , further comprising:
etching the chalcogenide layer to leave portions of the chalcogenide layer over only a first wordline at an edge of the fuse array.