Apparatuses with an embedded combination logic circuit for high speed operations
View Patent ↗Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
1. An apparatus comprising:
a first-in-first-out stage comprising an combination logic circuit;
a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage; and
a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage,
wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
2. The apparatus of claim 1 , wherein the first-in-first-out stage further comprises:
a NAND gate configured to receive the push signal and a select signal, and to provide a latch signal based, at least in part, on the push signal and the select signal,
a latch configured to provide the input data to the combination logic circuit based, at least in part, on the latch signal.
3. The apparatus of claim 1 , wherein the first-in-first-out stage further comprises:
an output inverter configured to receive the output data from the combination logic circuit and provide the output data based, at least in part, on the pop signal.
4. The apparatus of claim 3 , wherein the first-in-first-out stage further comprises:
a NAND gate configured to receive the pop signal and a select signal, and to selectively enable the output inverter to provide the output data based, at least in part, on the pop signal and the select signal.
5. The apparatus of claim 1 , wherein the combination logic circuit comprises a plurality of XOR gates configured to determine whether the input data contains a parity error.
6. The apparatus of claim 5 , wherein the plurality of XOR gates comprises a five-stage XOR tree.
7. The apparatus of claim 1 , wherein the push signal and the pop signal are temporally offset by a predetermined time period.
8. An apparatus comprising:
a first-in-first-out stack comprising a first first-in-first-out stage and a second first-in-first-out stage, the first and second first-in-first-out stages each comprising an combination logic circuit;
a input ring counter circuit coupled to the first and second first-in-first-out stages and configured to selectively provide a respective push signal to each of the first and second first-in-first-out stages; and
a output ring counter circuit coupled to the first and second first-in-first-out stages and configured to selectively provide a respective pop signal to the first and second first-in-first-out stages,
wherein the first and second first-in-first-out stages are configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the respective push signal and to provide the output data based on the calculations responsive to receiving the respective pop signal.
9. The apparatus of claim 8 , further comprising a common data input line coupled to the first and second first-in-first-out stages and configured to provide the input data to the first and second first-in-first-out stages.
10. The apparatus of claim 9 , wherein the input ring counter circuit is configured to provide a first push signal to the first first-in-first-out stage responsive to a first set of input data being provided on the common data input line, and a second push signal to the second first-in-first-out stage responsive to a second set of input data being provided on the common data input line.
11. The apparatus of claim 9 , wherein the first and second first-in-first-out stages each further comprises:
a latch having a data input terminal, wherein the common data input line is coupled to the data input terminal.
12. The apparatus of claim 11 , wherein the first and second first-in-first-out stages each further comprises:
a NAND gate configured to receive the respective push signal and to provide a latch signal to the latch responsive to receiving the respective push signal,
wherein the latch provides the input data to the combination logic circuit responsive to receiving the latch signal.
13. The apparatus of claim 12 , wherein the first and second first-in-first-out stages each further comprises:
an output inverter configured to receive the output data from the combination logic circuit, the output inverter coupled to a common node of the first and second first-in-first-out stages;
a second NAND gate configured to receive the respective pop signal and to selectively enable the output inverter to provide the output data to a common node.
14. The apparatus of claim 8 , wherein the combination logic circuit is configured to perform a parity error calculation.
15. An apparatus comprising:
an combination logic circuit configured to perform operations on input data to generate output data;
a latch coupled to the combination logic circuit and configured to provide the input data to the combination logic circuit based, at least in part, on a push signal;
an output inverter coupled to the combination logic circuit and configured to receive the output data from the combination logic circuit and to provide the output data responsive to a pop signal.
16. The apparatus of claim 15 , further comprising:
a NAND gate configured to receive the push signal and to provide a latch signal to the latch, wherein the latch is configured to provide the input data to the combination logic circuit responsive to the latch signal.
17. The apparatus of claim 15 , further comprising a NAND gate configured to receive the push signal and to selectively enable the output inverter to provide the output data.
18. The apparatus of claim 15 , wherein the push signal is provided by a input ring counter circuit.
19. The apparatus of claim 15 , wherein the pop signal is provided by a output ring counter circuit.
20. The apparatus of claim 15 , wherein the pop signal is temporally offset from the push signal by a predetermined period of time.