Error correction code (ECC) operations in memory

1. A method for performing an error correction code (ECC) operation, comprising:

generating a bose-chaudhuri-hocquenghem (BCH) codeword, via a BCH encoder, based on a number of BCH parity bits and a number of low density parity check (LDPC) codewords in response to one of the number of LDPC codewords failing a LDPC decoding operation; and

performing a BCH decoding operation using the BCH codeword to correct errors associated with an uncorrectable LDPC codeword.

2. The method of claim 1 , wherein generating the BCH codeword includes summing the number of LDPC codewords.

3. The method of claim 1 , wherein the BCH decoding operation includes a correction power of ≥8 and ≤12.

4. The method of claim 1 , wherein performing the BCH decoding operation includes generating a BCH codeword based on the number of LDPC codewords combined with BCH parity bits created during an encoding operation.

5. The method of claim 1 , wherein the method includes executing the BCH decoding operation in response to one of the number of LDPC codewords failing the LDPC decoding operation and a remaining number of the number of LDPC codewords passing the LDPC decoding operation.

6. An apparatus, comprising:

a memory device;

a controller coupled to the memory device configured to:

generate a number of low density parity check (LDPC) codewords and bose-chaudhuri-hocquenghem (BCH) parity bits during an encoding operation;

execute a LDPC decoding operation, wherein the decoding operation includes performing a LDPC decoding operation on each of the number of LDPC codewords;

generate a BCH codeword, based on the number of LDPC codewords and BCH parity bits based on user data of a write operation, via a BCH encoder, in response to one of the number of LDPC codewords failing the LDPC decoding operation; and

perform a BCH decoding operation using the BCH codeword to correct errors associated with an uncorrectable LDPC codeword.

7. The apparatus of claim 6 , wherein 4 LDPC codewords are generated.

8. The apparatus of claim 6 , wherein each LDPC codeword of the number of LDPC codewords is 1 KB.

9. The apparatus of claim 7 , wherein the BCH codeword is 1 KB.

10. The apparatus of claim 7 , wherein a success message is sent in response to all of the number of LDPC codewords passing the LDPC decoding operation.

11. An apparatus comprising:

a memory device;

a controller coupled to the memory device configured to:

split user data into a number of portions and perform a low density parity check (LDPC) encoding operation on the number of portions to create a number of LDPC codewords;

execute an exclusive OR (XOR) operation on the number of LDPC codewords;

generate, during a bose-chaudhuri-hocquenghem (BCH) encoding operation, via a BCH encoder, a BCH codeword based on a result of the XOR operation and BCH parity bits based on user data of a write operation in response to one of the number of LDPC codewords failing a LDPC decoding operation; and

perform a BCH decoding operation using the BCH codeword to correct errors associated with an uncorrectable LDPC codeword.

12. The apparatus of claim 11 , wherein a min-sum decoding is applied to the number of LDPC codewords.

13. The apparatus of claim 11 , wherein the number of LDPC codewords are summed up and concatenated with a t-correcting BCH codeword.

14. The apparatus of claim 11 , wherein an overall error floor of the encoding operation and the BCH decoding operation is below 1E-12.

15. A method for performing an error correction code (ECC) operation, comprising:

executing a number of low density parity check (LDPC) decoding operations on a number of LDPC codewords;

sending a success message in response to all of the number of LDPC codewords passing the number of LDPC decoding operations;

sending a failure message in response to two or more of the number of LDPC codewords failing the number of LDPC decoding operations; and

executing a bose-chaudhuri-hocquenghem (BCH) decoding operation in response to one of the number of LDPC codewords failing the LDPC decoding operation and a remaining number of the number of LDPC codewords passing the LDPC decoding operation, wherein the BCH decoding operation includes:

generating, via a BCH encoder, a BCH codeword based on the number of LDPC codewords and BCH parity bits based on user data of a write operation; and

decoding the BCH codeword using a BCH decoder to correct errors associated with an uncorrectable LDPC codeword.

16. The method of claim 15 , wherein the method includes reducing an overall BCH overhead by 4 times.

17. The method of claim 15 , wherein the BCH decoding operation includes a correction power of ≥8 and ≤12.

18. The method of claim 15 , wherein executing the BCH decoding operation includes using a BCH codeword being ≤14 bits and a number of BCH parity bits that are ≤14 times a correction power of the BCH decoding operation.

19. The method of claim 15 , wherein the method includes the number of LDPC decoding operations being concatenated with a t-correcting BCH decoding operation.

20. The method of claim 19 , wherein concatenating the t-correcting BCH code with the number of LDPC decoding operations, a combined decoding error floor of the number of LDPC decoding operations and BCH decoding operations is reduced.

21. An apparatus, comprising:

a memory device;

a controller coupled to the memory device configured to:

generate a number of low density parity check (LDPC) codewords via a LDPC encoder and bose-chaudhuri-hocquenghem (BCH) parity bits via a BCH encoder from user data of a write operation during an encoding operation;

perform a number of LDPC decoding operations on the number of LDPC codewords; and

execute a BCH decoding operation via a BCH decoder using a BCH codeword based on the number of LDPC codewords and BCH parity bits to correct errors associated with an uncorrectable LDPC codeword of the number of LDPC codewords.

22. The apparatus of claim 21 , wherein the user data is split into a number of portions and a number of encoding operations are performed on the number of portions.

23. The apparatus of claim 22 , wherein the BCH codeword is based on a result of the XOR operation.

24. The apparatus of claim 21 , wherein the number of LDPC codewords generated is 4.

25. The apparatus of claim 21 , wherein an exclusive OR (XOR) operation is executed on the number of LDPC codewords in response to one of the number of LDPC codewords failing the number of LDPC decoding operations.