IP Library Granted Patent US 9,899,451
Granted Patent B2
US 9,899,451 · App. 15/155,433 · Granted Feb 20, 2018

Array of cross point memory cells and methods of forming an array of cross point memory cells

Inventors: Fabio Pellizzer (Boise, ID); Stephen W. Russell (Boise, ID); Tony M. Lindenberg (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/2472H01L27/2427H01L27/2463H01L45/04H01L45/06H01L45/065H01L45/126H01L45/1233H01L45/144H01L45/146H01L45/147H01L45/1675
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,899,451
App. No.
15/155,433
Granted
Feb 20, 2018
Kind
B2
Abstract

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

Claims (30)

1. An array of cross point memory cells, comprising:

spaced lower first lines, spaced upper second lines which cross the first lines above the lower first lines, and a multi-resistive state region elevationally between the first and second lines where such cross, individual of the memory cells comprising individual of the lower first lines, individual of the upper second lines, and individual of the multi-resistive state regions elevationally there-between where the individual first and second lines cross; and

the individual multi-resistive state regions in the individual memory cells comprising upper multi-resistive state material and lower multi-resistive state material below the upper multi-resistive state material, the upper multi-resistive state material and the lower multi-resistive state material being electrically coupled to one another within the individual memory cells, the lower multi-resistive state material having opposing edges in a vertical cross-section within the individual memory cells, the upper multi-resistive state material having opposing edges in the vertical cross-section within the individual memory cells that are laterally offset relative to the opposing edges of the lower multi-resistive state material in the vertical cross-section within the individual memory cells.

2. The array of claim 1 wherein the lower and upper multi-resistive state materials are of the same composition relative one another.

3. The array of claim 1 wherein the lower and upper multi-resistive state materials are of different compositions relative one another.

4. The array of claim 1 wherein the lower and upper multi-resistive state materials are directly against one another.

5. The array of claim 1 wherein the lower and upper multi-resistive state materials are not directly against one another.

6. The array of claim 1 comprising at least one of metal material and semi-metal material elevationally between the lower and upper multi-resistive state materials.

7. The array of claim 6 wherein the at least one of metal material and semi-metal material is intrinsically of higher conductivity than each of the lower and upper multi-resistive state materials when each is programmed to its highest conductivity state.

8. The array of claim 6 wherein the at least one comprises metal material.

9. The array of claim 6 wherein the at least one comprises semi-metal material.

10. The array of claim 6 wherein the at least one of metal material and semi-metal material is intrinsically not capable of being programmed to multi-resistive states.

11. The array of claim 1 comprising:

lower intervening material comprising at least one of metal material and semi-metal material elevationally between the lower and upper multi-resistive state materials; and

upper intervening material comprising at least one of metal material and semi-metal material elevationally between the lower and upper multi-resistive state materials and over the lower intervening material, the lower and upper intervening materials being of different compositions relative one another.

12. The array of claim 11 wherein,

the upper multi-resistive state material is directly against the upper intervening material; and

the upper intervening material being intrinsically of higher conductivity than each of the lower and upper multi-resistive state materials when each is programmed to its highest conductivity state.

13. The array of claim 1 wherein the upper multi-resistive state material and the lower multi-resistive state material have different thicknesses.

14. The array of claim 1 wherein the upper multi-resistive state material and the lower multi-resistive state material have the same thickness.

15. The array of claim 1 wherein the lower and upper multi-resistive state materials are of the same composition relative one another, the lower and upper multi-resistive state materials not being directly against one another.

16. The array of claim 1 wherein the lower and upper multi-resistive state materials are of the different compositions relative one another, the lower and upper multi-resistive state materials not being directly against one another.

17. An array of cross point memory cells, comprising:

spaced lower first lines, spaced upper second lines which cross the first lines above the lower first lines, and a multi-resistive state region elevationally between the first and second lines where such cross, individual of the memory cells comprising individual of the lower first lines, individual of the upper second lines, and individual of the multi-resistive state regions elevationally there-between where the individual first and second lines cross; and

the individual multi-resistive state regions in the individual memory cells comprising upper multi-resistive state material and lower multi-resistive state material below the upper multi-resistive state material, the upper multi-resistive state material and the lower multi-resistive state material being electrically coupled to one another within the individual memory cells, the lower and upper multi-resistive state materials being of different compositions relative one another and being directly against one another, the lower multi-resistive state material having opposing edges in a vertical cross-section within the individual memory cells, the upper multi-resistive state material having opposing edges in the vertical cross-section within the individual memory cells that are laterally offset relative to the opposing edges of the lower multi-resistive state material in the vertical cross-section within the individual memory cells.

18. The array of claim 17 wherein the upper multi-resistive state material and the lower multi-resistive state material have different thicknesses.

19. The array of claim 17 wherein the upper multi-resistive state material and the lower multi-resistive state material have the same thickness.

20. An array of cross point memory cells, comprising:

spaced lower first lines, spaced upper second lines which cross the first lines above the lower first lines, and a multi-resistive state region elevationally between the first and second lines where such cross, individual of the memory cells comprising the individual of the lower first lines, individual of the upper second lines, and individual of the multi-resistive state regions elevationally there-between where the individual first and second lines cross; and

the individual multi-resistive state regions in the individual memory cells comprising upper multi-resistive state material and lower multi-resistive state material below the upper multi-resistive state material, the upper multi-resistive state material and the lower multi-resistive state material being electrically coupled to one another within the individual memory cells, the lower and upper multi-resistive state materials being of the same composition relative one another and being directly against one another, the lower multi-resistive state material having opposing edges in a vertical cross-section within the individual memory cells, the upper multi-resistive state material having opposing edges in the vertical cross-section within the individual memory cells that are laterally offset relative to the opposing edges of the lower multi-resistive state material in the vertical cross-section within the individual memory cells.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
Continuity (2)
Division 14293577 · Jun 2, 2014
Related Publication 20160260777A1 · Sep 8, 2016