IP Library Granted Patent US 9,911,643
Granted Patent B2
US 9,911,643 · App. 15/182,462 · Granted Mar 6, 2018

Semiconductor constructions and methods of forming intersecting lines of material

Inventors: Hongqi Li (Boise, ID); Gowrisankar Damarla (Boise, ID); Robert J. Hanson (Boise, ID); Jin Lu (Boise, ID); Shyam Ramalingam (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76816H01L21/76877H01L23/481H01L23/528H01L23/5226H01L23/5283H01L2924/0002
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Quick Facts
Patent No.
US 9,911,643
App. No.
15/182,462
Granted
Mar 6, 2018
Kind
B2
Abstract

Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

Claims (33)

1. A method of forming intersecting lines of material, comprising:

forming first and second trenches that intersect with one another at an intersection;

the first trench having primarily a first width, and having narrowed regions directly against the second trench and on opposing sides of the second trench from one another, the narrowed regions having lateral dimensions along and parallel with the second trench, and having longitudinal dimensions orthogongal to the lateral dimensions, the longitudinal dimensions being, less than or equal to the lateral dimensions; and

depositing material within the first and second trenches to substantially entirely fill the first and second trenches.

2. The method of claim 1 wherein the material is an electrically conductive material.

3. The method of claim 1 wherein the material is an electrically insulative material.

4. The method of claim 1 wherein the material is a semiconductor material.

5. The method of claim 1 wherein the material comprises one or more metals.

6. The method of claim 1 wherein the second trench has primarily a second width, and wherein the first and second widths are substantially the same as one another.

7. The method of claim 6 wherein the first and second widths are “a”, the narrowed regions have widths “b”, and the material is deposited to a thickness of about

a

1

+

k

2

2

,

where

k

=

b

a

.

8. A method of forming a semiconductor construction, comprising:

forming first and second electrically conductive lines that intersect with one another at an intersection; the first line having primarily a first width, and having narrowed regions directly against the second line and on opposing sides of the second line from one another, the narrowed regions having lateral dimensions along and parallel with the second line and longitudinal dimensions orthogonal to the lateral dimensions, the longitudinal dimensions being less than or equal to the lateral dimensions, the lateral dimensions being within a range of from about 30% of the first width to about 80% of the first width; and

forming electrically conductive contacts along the first line and directly electrically coupled to the first line, one of the electrically conductive contacts being directly against the intersection.

9. The method of claim 8 wherein the electrically conductive contacts along the first line and the intersection are spaced from one another by a common distance.

10. The method of claim 8 wherein the electrically conductive lines comprise metal.

11. The method of claim 8 wherein the electrically conductive contacts are also along the second line and directly electrically coupled to the second line in regions other than the intersection.

12. The method of claim 8 wherein the narrowed regions are substantially mirror images of one another across a plane along the second line.

13. The method of claim 8 wherein the narrowed regions are not substantially mirror images of one another across a plane along the second line.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
Continuity (2)
Division 13975722 · Aug 26, 2013
Related Publication 20160293482A1 · Oct 6, 2016