Apparatuses including memory section control circuits with global drivers
View Patent ↗Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
1. An apparatus comprising:
a plurality of memory sections including a first memory section, each of the memory section including a plurality of word lines;
a first WL driver coupled to the first memory section to select at least one of the plurality of word lines; and
a first global driver outputting a first voltage to the first WL driver when the first memory section is activated and outputting a second voltage lower than the first voltage to the first WL driver when the first memory section is not activated.
2. The apparatus as claimed in claim 1 , wherein the first global driver outputs the first voltage when the first memory is to be refreshed and outputs the second voltage when the first memory is not to be refreshed.
3. The apparatus as claimed in claim 2 , further comprising:
a first decoder voltage supply supplying the first voltage to the first global driver when the first memory section is activated and supplying the second voltage when the first memory section is not activated.
4. The apparatus as claimed in claim 1 , further comprising:
a first decoder voltage supply supplying the first voltage to the first global driver when the first memory section is activated and supplying the second voltage when the first memory section is not activated.
5. The apparatus as claimed in claim 1 , further comprising:
a first phase decoder coupled to the first WL driver to select one of the word lines based on a signal from the first phase decoder and the first voltage from the first global decoder.
6. The apparatus as claimed in claim 1 , wherein the plurality of memory sections includes a second memory section;
a second WL driver coupled to the second memory section to select at least one of the plurality of word lines; and
a second global driver outputting the first voltage to the second WL driver when the second memory section is activated and outputting the second voltage to the second WL driver when the second memory section is not activated.
7. The apparatus as claimed in claim 6 , wherein the second global driver outputs the first voltage when the second memory is to be refreshed and outputs the second voltage when the second memory is not to be refreshed.
8. The apparatus as claimed in claim 7 , further comprising:
a second decoder voltage supply supplying the first voltage to the second global driver when the second memory section is activated and supplying the second voltage when the second memory section is not activated.
9. The apparatus as claimed in claim 6 , further comprising:
a second decoder voltage supply supplying the first voltage to the second global driver when the second memory section is activated and supplying the second voltage when the second memory section is not activated.
10. The apparatus as claimed in claim 1 , further comprising:
a second phase decoder coupled to the second WL driver to select one of the word lines based on a signal from the second phase decoder and the first voltage from the second global decoder.
11. An apparatus comprising:
a plurality of memory sections including first memory sections activated in a self-refresh mode and second memory sections inactivated in the self-refresh mode;
a plurality of WL drivers including first WL drivers each coupled to respective one of the first memory sections and second WL drivers each coupled to respective one of the second memory sections; and
a plurality of global drivers including first global drivers each coupled to respective one of the first WL drivers and supplying a first voltage to the respective one of the first WL drivers in the self-refresh mode, and including second global drivers each coupled to respective one of the second WL drivers and supplying a second voltage lower than the first voltage to the respective one of the second WL drivers in the self-refresh mode.
12. The apparatus as claimed in claim 11 , further comprising:
a self-refresh controller generating a refresh address to refresh the first memory sections except for the second memory sections.
13. The apparatus as claimed in claim 11 , wherein the plurality of memory sections includes third memory sections activated in a self-refresh mode,
wherein the plurality of WL drivers further includes third WL drivers each coupled to respective one of the third memory sections, and
wherein the plurality of global drivers further includes third global drivers each coupled to a respective one of the third WL drivers and supplying the first voltage to the respective one of the third WL drivers in the self-refresh mode.
14. The apparatus as claimed in claim 13 , further comprising:
a self-refresh controller generating refresh addresses for the first memory sections and the third memory sections to alternate refreshing multiple rows at a time.
15. The apparatus as claimed in claim 13 , further comprising:
a self-refresh controller generating refresh addresses for the first memory sections and the third memory sections to alternate refreshing rows one at a time.
16. The apparatus as claimed in claim 11 , wherein the first global drivers and the third global drivers supply the first voltage to the respective one of the first WL drivers and to the respective one of the third WL drivers, respectively, until the first and third memory sections have been refreshed.
17. An apparatus comprising:
a plurality of memory sections each includes a plurality of word lines;
a plurality of WL drivers each coupled to respective one of the plurality of memory sections and each including a plurality of word line drivers each coupled to respective one of the plurality of word lines; and
a plurality of global drivers each coupled to respective one of the plurality of WL drivers and each supplying a first voltage to the respective one of the plurality of WL drivers when at least one of the plurality of word lines of the respective one of the plurality of drivers is selected, and each supplying a second voltage lower than the first voltage to the respective one of the plurality of WL drivers when none of the plurality word lines of the respective one of the plurality of drivers is not selected.
18. The apparatus as claimed in claim 17 , wherein each of the plurality of global drivers is configured to receive a respective enable signal and wherein each of the plurality of global drivers is configured to supply the first voltage or the second voltage to the respective one of the plurality of WL drivers responsive to the respective enable signal.
19. The apparatus as claimed in claim 17 , a plurality of phase decoders, each coupled to a respective plurality of word line drivers and configured to provide a respective phase signal to each of the respective plurality of word line drivers.
20. The apparatus as claimed in claim 17 , wherein each of the plurality of word line drivers configured to provide the respective one of the plurality of word lines with a deactivated word line voltage responsive to the second voltage.