Plate defect mitigation techniques
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.
1. A method of operating a ferroelectric memory cell, comprising:
identifying a first cell plate included in a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
identifying a second cell plate that is adjacent to the first cell plate and included in a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent, wherein the first cell plate is in a last position in the first cell plate group and the second cell plate is in a first position in the second cell plate group; and
selecting the first cell plate and the second cell plate based at least in part on a short between the first cell plate and the second cell plate.
2. The method of claim 1 , wherein the short comprises:
a first current level of the first cell plate and a second current level of the second cell plate, wherein the first current level results from applying a voltage to the first cell plate and the second current level results from applying the voltage to the second cell plate.
3. The method of claim 1 , further comprising:
reading information from the first cell plate and the second cell plate based at least in part on reading information from a first sense amp in electronic communication with the first cell plate and a second sense amp in electronic communication with the second cell plate.
4. The method of claim 1 , further comprising:
reading information from the first cell plate and the second cell plate in combination based at least in part on the selection.
5. A method of operating a ferroelectric memory cell, comprising:
identifying a first cell plate included in a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
identifying a second cell plate that is adjacent to the first cell plate and included in a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
identifying a third cell plate included in a third cell plate group;
identifying a fourth cell plate included in the second cell plate group or the third cell plate group;
identifying the third cell plate adjacent to the fourth cell plate;
selecting the first cell plate and the second cell plate based at least in part on a short between the first cell plate and the second cell plate, and
selecting the third cell plate and the fourth cell plate as a pair based at least in part on the short between the first cell plate and the second cell plate.
6. The method of claim 5 , wherein the third cell plate is included in the third cell plate group and the fourth cell plate is included in the second cell plate group.
7. The method of claim 6 , wherein the third cell plate is in a first position in the third cell plate group and the fourth cell plate is in a last position in the second cell plate group.
8. An electronic memory apparatus, comprising:
a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
a first cell plate included in the first cell plate group; and
a second cell plate adjacent to the first cell plate and included in the second cell plate group, wherein the first cell plate and the second cell plate are in electronic communication via a short between the first cell plate and the second cell plate, wherein the first cell plate is in a last position in the first cell plate group and the second cell plate is in a first position in the second cell plate group.
9. The electronic memory apparatus of claim 8 , wherein the electronic communication is based at least in part on a proximity of the first cell plate to the second cell plate.
10. The electronic memory apparatus of claim 8 , further comprising:
a first digit line in electronic communication with the first cell plate and a first sense amp via a first transistor.
11. The electronic memory apparatus of claim 10 , further comprising:
a second digit line in electronic communication with the second cell plate and a second sense amp via a second transistor.
12. An electronic memory apparatus, comprising:
a first cell plate included in a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
a second cell plate included in a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent, wherein the first cell plate is in a last position in the first cell plate group and the second cell plate is in a first position in the second cell plate group;
a first digit line in electronic communication with the first cell plate and a first sense amp via a first transistor;
a second digit line in electronic communication with the second cell plate and a second sense amp via a second transistor; and
a controller in electronic communication with the first sense amp and the second sense amp, wherein the controller is operable to:
select the first cell plate and the second cell plate based at least in part on a short between the first cell plate and the second cell plate; and
read information from at least one of the first sense amp and the second sense amp based at least in part on the selection.
13. The electronic memory apparatus of claim 12 , wherein the first cell plate group is adjacent to the second cell plate group.
14. The electronic memory apparatus of claim 12 , wherein the controller is operable to:
select the first cell plate from the first cell plate group and the second cell plate from the second cell plate group.
15. The electronic memory apparatus of claim 12 , wherein the short is based at least in part on a position of the first cell plate in the first cell plate group relative to the second cell plate in the second cell plate group.
16. An electronic memory apparatus, comprising:
a first cell plate included in a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
a second cell plate included in a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
a first digit line in electronic communication with the first cell plate and a first sense amp via a first transistor;
a second digit line in electronic communication with the second cell plate and a second sense amp via a second transistor;
a third cell plate included in the first cell plate group;
a fourth cell plate included in the first cell plate group; and
a controller in electronic communication with the first sense amp and the second sense amp, wherein the controller is operable to:
select the first cell plate and the second cell plate based at least in part on a short between the first cell plate and the second cell plate;
select the third cell plate and the fourth cell plate based at least in part on a spatial relationship between the first cell plate and the second cell plate; and
read information from at least one of the first sense amp and the second sense amp based at least in part on the selection.
17. The electronic memory apparatus of claim 16 , wherein the third cell plate is adjacent to the first cell plate and the fourth cell plate.