IP Library Granted Patent US 9,722,178
Granted Patent B2
US 9,722,178 · App. 15/206,556 · Granted Aug 1, 2017

Resistive memory having confined filament formation

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Quick Facts
Patent No.
US 9,722,178
App. No.
15/206,556
Granted
Aug 1, 2017
Kind
B2
Abstract

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an are enclosed by the oxide material formed in the opening.

Claims (32)

1. A method of processing a resistive memory cell, comprising:

forming a stack having a resistive memory material, a silicon material formed on the resistive memory material, an oxide material formed on the silicon material; forming an opening in the silicon material and the oxide material of the stack;

selectively forming a metal material in a lower portion of the opening on opposing sidewalls of the silicon material and a lower portion of opposing sidewalls of the oxide material such that:

the metal material is in contact with an upper surface of the resistive memory material, an entirety of the opposing sidewalls of the silicon material, and the lower portion of opposing sidewalls of the oxide material;

the metal material is adjacent a lower portion of the opening; and

the metal material does not form adjacent an upper sidewall of the oxide material; and

oxidizing all of the metal material; forming an ion source material in the opening in an area enclosed by the oxidized metal material and contacting opposing upper sidewalls of the oxide material;

wherein the oxidized metal material confines filament formation in the resistive memory cell to an area enclosed by the oxidized metal material.

2. The method of claim 1 , wherein the method includes forming the ion source material in the opening such that the ion source material completely fills the area enclosed by the oxidized metal material.

3. The method of claim 1 , wherein the area enclosed by the oxidized metal material has a width of 5 to 15 nanometers.

4. A method of processing a resistive memory cell, comprising:

forming a stack having a resistive memory material, a silicon material on the resistive memory material, and a first oxide material on the silicon material; forming an opening in the silicon material and the first oxide material of the stack;

forming a second oxide material in a lower portion of the opening on opposing sidewalls of the silicon material and on a lower portion of opposing sidewalls of the first oxide material by:

selectively forming a metal material in the lower portion of the opening on opposing sidewalls of the silicon material and on the lower portion of opposing sidewalls of the first oxide material such that the metal material is in contact with an upper surface the resistive memory material, an entirety of the opposing sidewalls of the silicon material, and the lower portion of the opposing sidewalls of the first oxide material; and

oxidizing all of the metal material; and

forming an ion source material in the opening contacting opposing sidewalls of the oxide material and opposing sidewalls of the second oxide material, wherein the ion source material is copper telluride or silver sulfide.

5. The method of claim 4 , wherein the second oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the second oxide material.

6. The method of claim 4 , wherein:

the stack includes an electrode on which the resistive memory material is formed.

7. A resistive memory cell, comprising:

a vertical stack having:

a resistive memory material;

a silicon material on and directly contacting the resistive memory material;

an oxide material on the silicon material; and

an oxidized metal material, wherein:

the oxidized material is formed between opposing sidewalls of the silicon material and in contact with an upper surface of the resistive memory material; and

the oxidized metal material is formed between lower portions of opposing sidewalls of the oxide material; further comprising an ion source material formed in an area enclosed by the oxidized metal material and contacting opposing upper sidewalls of the oxide material.

8. The resistive memory cell of claim 7 , wherein the oxidized metal material is formed on a wall of the silicon material.

9. The resistive memory cell of claim 8 , wherein the ion source material is on the resistive memory material and formed on a wall of the oxidized metal material.

10. The resistive memory cell of claim 8 , wherein the area enclosed by the oxidized metal material has a width of 5 to 15 nanometers.

11. The resistive memory cell of claim 8 , wherein the oxidized metal material is a copper oxide material.

12. The resistive memory cell of claim 7 , wherein the silicon material is a silicon nitride material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2016
From: MARSH, EUGENE P.; LIU, JUN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039120/0709 →