IP Library Granted Patent US 9,960,258
Granted Patent B2
US 9,960,258 · App. 15/207,275 · Granted May 1, 2018

Methods of forming transistor gates

Inventor: Yongjun Jeff Hu (Boise, ID)
Assignee: Micron Technology, Inc.
H01L29/66833H01L21/28273H01L21/28282H01L27/115H01L27/1157H01L27/11521H01L27/11524H01L29/4234H01L29/66825H01L29/792
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Quick Facts
Patent No.
US 9,960,258
App. No.
15/207,275
Granted
May 1, 2018
Kind
B2
Abstract

Some embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Claims (23)

1. A method of forming a charge storage transistor gate and a field effect transistor (FET) gate, comprising:

forming a pair of spaced apart gate stacks over a semiconductor substrate; one of the gate stacks being defined as an FET gate stack, and another of gate stacks being defined as a charge storage transistor gate stack; the FET gate stack comprising a gate dielectric material, a gate material over the gate dielectric material, an electrically insulative material over the gate material, and a sacrificial material over the electrically insulative material; the charge storage transistor gate stack comprising the gate dielectric material, the gate material over the gate dielectric material, the electrically insulative material over the gate material, and the sacrificial material over the electrically insulative material;

removing the sacrificial material from the FET and charge storage transistor gate stacks;

etching through the electrically insulative material of the FET gate stack to the gate material of the FET gate stack; and

after etching through the electrically insulative material, forming a conductive material over the FET gate stack and over the charge storage transistor gate stack, the conductive material physically contacting the gate material of the FET gate stack, and being separated from the gate material of the charge storage transistor gate stack by only the electrically insulative material.

2. The method of claim 1 wherein the sacrificial material comprises silicon.

3. The method of claim 1 wherein the gate material consists of conductively-doped silicon.

4. The method of claim 3 wherein the conductive material comprises at least one metal.

5. The method of claim 3 wherein the conductive material comprises at least one material selected from the group consisting of metal and metal nitrides, and has a high work function.

6. A method of forming a charge storage transistor gate and a field effect transistor (FET) gate, comprising:

forming a FET gate stack spaced apart from a charge storage transistor gate stack, each gate stack comprising gate material over a semiconductor substrate and electrically insulative material over the gate material; and

forming an opening only through the electrically insulative material of the FET gate stack to reach the gate material while protecting the electrically insulative material of the charge storage transistor gate stack.

7. The method of claim 6 wherein the forming of the opening comprises etching through only a portion of the electrically insulative material of the FET gate stack.

8. The method of claim 6 wherein the electrically insulative material comprises at least two separate and discrete layers.

9. The method of claim 6 wherein the forming of the opening comprises exposing at least a portion of the gate material of the FET gate stack.

10. A method of forming a charge storage transistor gate and a field effect transistor (FET) gate, comprising:

forming a FET gate stack spaced apart from a charge storage transistor gate stack, each gate stack comprising gate material over a semiconductor substrate;

forming electrically insulative material over at least a portion of each gate material of the FET gate stack and the charge storage transistor gate stack;

forming an electrically conductive material in contact with the gate material of the FET gate stack while protecting the gate material of the charge storage transistor gate stack; and

forming a conductive layer over the electrically conductive material.

11. The method of claim 10 wherein the forming of the electrically insulative material comprises forming the electrically insulative material over an entirety of the gate material of the charge storage transistor gate stack.

12. The method of claim 10 wherein the forming of the electrically insulative material comprises forming the electrically insulative material over only a portion of the gate material of the FET gate stack.

13. The method of claim 10 wherein the forming of the electrically conductive material comprises a composition different from the gate material.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 068884/0654 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050676/0782 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046635/0634 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 26, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 039841/0207 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Aug 25, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 039824/0681 →
Continuity (5)
Division 14225053 · Mar 25, 2014
Division 13605848 · Sep 6, 2012
Division 12986487 · Jan 7, 2011
Division 12128404 · May 28, 2008
Related Publication 20160322478A1 · Nov 3, 2016