Methods and apparatus for checking the results of characterized memory searches
Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
1. A method for accelerating a memory hard application, the method comprising:
selecting a characterized rate based on a solution density function associated with the memory hard application;
searching a characterized memory at the characterized rate with a first processor for one or more solutions to the memory hard application;
validating the one or more solutions with a validation memory at a specified rate with a second processor; and
responsive to successful validation of at least one solution, providing the at least one solution to the memory hard application via the second processor;
wherein the characterized rate is selected at least to increase memory bandwidth of the characterized memory.
2. The method of claim 1 , wherein the characterized rate is further selected to reduce power consumption of the characterized memory.
3. The method of claim 1 , further comprising reading a data structure from the characterized memory that indicates a level of actual or predicted performance over a range of operational parameters;
wherein the characterized rate is further selected based on the solution density function and the data structure.
4. The method of claim 1 , further comprising monitoring a historic performance for the memory hard application;
wherein the characterized rate is further selected based on the solution density function and the historic performance.
5. The method of claim 1 , further comprising storing a searchable data structure;
wherein the solution density function is calculated based on a probability that a valid solution for the memory hard application is found within the searchable data structure.
6. The method of claim 5 , wherein the searchable data structure stores a subset of a solution space for the memory hard application.
7. A method for accelerating a memory hard application, the method comprising:
selecting a characterized rate based on a solution density function associated with the memory hard application;
searching a characterized memory at the characterized rate with a first processor for one or more solutions to the memory hard application;
validating the one or more solutions with a validation memory at a specified rate with a second processor; and
responsive to successful validation of at least one solution, providing the at least one solution to the memory hard application via the second processor;
wherein:
the memory hard application has a threshold of error-tolerance; and
the characterized rate is selected based on a bit error rate (BER) that does not exceed the threshold of error-tolerance.
8. A method for accelerating a memory hard application, the method comprising:
determining a characterized rate via a testing procedure other than the memory hard application;
selecting the characterized rate based on a solution density function associated with the memory hard application;
searching a characterized memory at the characterized rate with a first processor for one or more solutions to the memory hard application;
validating the one or more solutions with a validation memory at a specified rate with a second processor; and
responsive to successful validation of at least one solution, providing the at least one solution to the memory hard application via the second processor.
9. The method of claim 8 , further comprising determining a characterized rate based on historic performance of the memory hard application.
10. The method of claim 8 , wherein the validating the one or more solutions with the validation memory at the specified rate is performed at a general compute bit error rate (BER) that does not exceed 1×10 −18 .
11. The method of claim 8 , further comprising reading a data structure from the characterized memory that indicates a level of actual or predicted performance over a range of operational parameters;
wherein the characterized rate is selected based on the solution density function and the data structure.
12. The method of claim 8 , further comprising monitoring a historic performance for the memory hard application;
wherein the characterized rate is selected based on the solution density function and the historic performance.
13. A method for accelerating a memory hard application, the method comprising:
selecting a characterized rate based on a solution density function associated with the memory hard application;
searching a characterized memory at the characterized rate with a first processor for one or more solutions to the memory hard application;
validating the one or more solutions with a validation memory at a specified rate with a second processor; and
responsive to successful validation of at least one solution, providing the at least one solution to the memory hard application via the second processor;
wherein the memory hard application comprises an asymmetric memory search.
14. The method of claim 13 , wherein a result of the asymmetric memory search is a proof-of-work (POW) for a cryptocurrency.
15. The method of claim 13 , further comprising storing a searchable data structure;
wherein the solution density function is calculated based at least on a probability that a valid solution for the memory hard application is found within the searchable data structure.
16. The method of claim 15 , wherein the searchable data structure stores a subset of a solution space for the memory hard application.
17. A memory apparatus configured to accelerate asymmetric memory applications, the memory apparatus comprising:
a validation processor;
a validation memory configured to store a validation data structure, where the validation processor is configured to access the validation memory at a specified rate;
one or more search processors; and
one or more search memories configured to store a searchable data structure, wherein the one or more search processors are configured to access the one or more search memories at one or more corresponding characterized rates; and
where the validation memory further comprises one or more instructions which when executed by the validation processor, cause the validation processor to, responsive to receiving a solution to the asymmetric memory application from a first processor of the one or more search processors:
validate the solution to the asymmetric memory application with the validation memory at the specified rate; and
responsive to successful validation of the solution, provide the solution to the asymmetric memory application;
wherein the first processor of the one or more search processors is configured to access a first memory of the one or more search memories at a first characterized rate selected to increase memory bandwidth of the first memory.
18. A memory apparatus configured to accelerate asymmetric memory applications, the memory apparatus comprising:
a validation processor;
a validation memory configured to store a validation data structure, where the validation processor is configured to access the validation memory at a specified rate;
one or more search processors;
one or more search memories configured to store a searchable data structure, where the one or more search processors are configured to access the one or more search memories at one or more corresponding characterized rates; and
where the validation memory further comprises one or more instructions which when executed by the validation processor, cause the validation processor to, responsive to receiving a solution to the asymmetric memory application from a first processor of the one or more search processors:
validate the solution to the asymmetric memory application with the validation memory at the specified rate; and
responsive to successful validation of the solution, provide the solution to the asymmetric memory application;
wherein:
the asymmetric memory application has a threshold of error-tolerance; and
the first characterized rate is selected based on a bit error rate (BER) that does not exceed the threshold of error-tolerance.
19. The memory apparatus of claim 18 , wherein:
the asymmetric memory application is a cryptocurrency mining application; and
the solution is a proof-of-work (POW) for a cryptocurrency.
20. The memory apparatus of claim 19 , wherein the validation memory further comprises one or more instructions which when executed by the validation processor, cause the validation processor to: transmit the solution to at least one peer device of the cryptocurrency mining application.