Use of outstanding command queues for separate read-only cache and write-read cache in a memory sub-system

1. A method comprising:

receiving a memory access request associated with data stored at a memory sub-system;

determining a type of a memory access workload based on the request;

determining whether the data is stored at a separate respective cache of the memory sub-system, the separate respective cache corresponding to the type of the memory access workload;

responsive to determining that the data is not stored at the separate respective cache of the memory sub-system, determining, by a processing device, a separate respective queue of a plurality of queues to store the request with other memory access requests for the data stored at the memory sub-system, the separate respective queue corresponding to the separate respective cache; and

storing the request at the determined separate respective queue with the other read memory access requests for the data stored at the memory sub-system.

2. The method of claim 1 , wherein determining the type of the memory access workload comprises determining whether the memory access workload is associated with sequential memory access operations, and wherein determining whether the data is stored at the separate respective cache of the memory sub-system comprises determining whether a separate respective content addressable memory (CAM) of the separate respective cache includes an identifier associated with the data.

3. The method of claim 2 , wherein the plurality of queues are associated with the separate respective cache and another plurality of queues are associated with another separate respective cache, and determining whether the data is stored at the separate respective cache of the memory sub-system further comprises determining whether any of the plurality of queues are associated with the identifier.

4. The method of claim 1 , wherein determining the separate respective queue of the plurality of queues to store the memory access request with other memory access requests for the data stored at the memory sub-system comprises:

determining an identifier associated with the data based on the memory access request, wherein the identifier comprises an address of the data; and

determining that the queue is assigned the identifier, the queue being assigned the identifier responsive to determining that the data included in a first memory access request of the other memory access requests is not found in the separate respective cache.

5. The method of claim 4 , further comprising determining that the queue is invalid and is not blocked prior to assigning the identifier to the queue.

6. The method of claim 1 , further comprising responsive to determining that the data is stored at the separate respective cache of the memory sub-system, storing the memory access request at another queue used to manage execution of memory access requests to access other data that is present in the separate respective cache.

7. The method of claim 1 , wherein determining whether the data is stored at the separate respective cache of the memory sub-system is based on whether a valid bit for the data is set in the separate respective cache.

8. The method of claim 1 , further comprising incrementing a respective counters associated with the separate respective queue in response to storing the memory access request in the separate respective queue.

9. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to:

receive a memory access request associated with data stored at a memory sub-system;

determine a type of a memory access workload based on the request;

determine whether the data is stored at a separate respective cache of the memory sub-system, the separate respective cache corresponding to the type of the memory access workload;

responsive to determining that the data is not stored at the separate respective cache of the memory sub-system, determine a separate respective queue of a plurality of queues to store the request with other memory access requests for the data stored at the memory sub-system, the separate respective queue corresponding to the separate respective cache; and

store the request at the determined separate respective queue with the other memory access requests for the data stored at the memory sub-system.

10. The system of claim 9 , wherein to determine whether the data is stored at the separate respective cache of the memory sub-system, the processing device is further to determine whether a separate respective content addressable memory (CAM) of the separate respective cache includes an identifier associated with the data.

11. The system of claim 10 , wherein the plurality of queues are associated with the separate respective cache and another plurality of queues are associated with another separate respective cache, and wherein to determine whether the data is stored at the separate respective cache of the memory sub-system, the processing device is further to determine whether any of the plurality of queues are associated with the identifier.

12. The system of claim 9 , wherein to determine the separate respective queue of the plurality of queues to store the memory access request with other memory access requests for the data stored at the memory sub-system the processing device is further to:

determine an identifier associated with the data based on the memory access request, wherein the identifier comprises an address of the data; and

determine that the queue is assigned the identifier, wherein the queue is assigned the identifier in response to determining that the data included in a first memory access request of the other memory access requests is not found in the separate respective cache.

13. The system of claim 12 , wherein the processing device is further to determine that the queue is invalid and is not blocked prior to assigning the identifier to the queue.

14. The system of claim 9 , wherein responsive to determining that the data is stored at the separate respective cache of the memory sub-system, the processing device is further to store the memory access request at another queue used to manage execution of memory access requests to access other data that is present in the separate respective cache.

15. The system of claim 9 , wherein to determine whether the data is stored at the separate respective cache of the memory sub-system the processing device is further to determine whether a valid bit for the data is set in the separate respective cache.

16. A method comprising:

determining that data requested by a plurality of memory access requests has been retrieved from a memory sub-system;

executing one or more fill operations to store the data at a cache line of a separate respective cache of the memory sub-system;

determining, by a processing device, a separate respective queue of a plurality of queues, wherein each separate respective queue of the plurality of queues corresponds to a respective cache line of a plurality of cache lines of the separate respective cache of the memory sub-system, and wherein determining the separate respective queue of a plurality of queues corresponds to the requested data; and

in response to executing the one or more fill operations to store the data at the cache line, executing the plurality of memory access requests at the determined queue in an order in which the plurality of memory access requests have been received by the memory sub-system.

17. The method of claim 16 , further comprising:

storing the data in a fill queue in the order the data is retrieved from a memory component of the memory sub-system; and

executing the fill operation by removing the data from the fill queue in the order the data was stored in the fill queue to store the data at the cache line of the separate respective cache of the memory sub-system.

18. The method of claim 16 , further comprising:

decrementing a fill counter for each of the one or more fill operations that have been executed.