Level width based dynamic program step characteristic adjustment

1. A system, comprising:

a memory component including a group of memory cells; and

a processing device coupled to the memory component and configured to:

determine a level width corresponding to the group of memory cells, wherein the level width is a sum of at least two level widths of at least two threshold voltage distributions corresponding to respective states to which the group of memory cells are programmed;

compare the determined level width to a target level width; and

in response to the determined level width being different than the target level width, adjust one or more program step characteristics to adjust the determined level width toward the target level width.

2. The system of claim 1 , wherein the one or more program step characteristics comprises at least one of a step size or a step duration of a programming signal applied to the group of memory cells.

3. The system of claim 2 , wherein the processing device is further configured to adjust the step size without adjusting the step duration to adjust the determined level width toward the target level width.

4. The system of claim 2 , wherein the processing device is further configured to adjust the step duration without adjusting the step size of the programming signal to adjust the determined level width toward the target level width.

5. The system of claim 1 , wherein the memory component comprises a plurality of pages of memory cells, and wherein the group of memory cells on which the level width is determined is one or more of the plurality of pages, the one or more pages being randomly selected for the level width determination.

6. The system of claim 1 , wherein the group of memory cells comprises multi-level cells (MLCs).

7. The system of claim 6 , wherein the group of cells comprises a plurality of pages of cells, and wherein the level width is determined for more than one of the plurality of pages of cells.

8. The system of claim 7 , wherein the level width is determined on a page by page basis for the plurality of pages.

9. A method, comprising:

determining a level width corresponding to a group of memory cells programmed via a programming signal having one or more program step characteristics, wherein the level width is a sum of level widths of at least two threshold voltage distributions corresponding to respective states to which the group of memory cells are programmed;

comparing the determined level width to a target level width;

in response to the determined level width being different than the target level width, adjusting the one or more program step characteristics to adjust the determined level width to an adjusted level width;

comparing the adjusted level width to the target level width; and

in response to the adjusted level width being different than the target level width, further adjusting the one or more program step characteristics to adjust the adjusted level width toward the target level width.

10. The method of claim 9 , wherein:

the one or more program step characteristics comprises a step size and a program step duration; and

the method further comprises increasing the step size and the program step duration each by a respective particular amount in response to determining that the determined level width satisfies a threshold pertaining to the target level width.

11. The method of claim 9 , wherein:

the one or more program step characteristics comprises a step size and a program step duration; and

the method further comprises decreasing the step size and the program step duration each by a respective particular amount in response to determining that the determined level width satisfies a threshold pertaining to the target level width.

12. The method of claim 9 , further comprising repeating a comparison of a previously adjusted level width to the target level width.

13. The method of claim 12 , wherein the method further comprises, in response to the previously adjusted level width being a different level width than the target level width, adjusting the one or more program step characteristics until the previously adjusted level width is a same level width as the target level width.

14. The method of claim 9 , wherein the level width is a sum of the widths of respective threshold voltage (Vt) distributions corresponding to respective states to which the group of cells are programmed, and wherein determining the level width comprises, for each of the Vt distributions:

determining voltages corresponding to respective first and second edges of the Vt distribution using an interpolation process based on a first read level voltage whose corresponding bit error rate (BER) is lower than a target BER and a second read level voltage whose corresponding BER is greater than the target BER; and

using the determined voltages corresponding to the respective first and second edges to determine a width of the Vt distribution.

15. A system, comprising:

a memory component including a plurality of memory cells; and

a processing device coupled to the memory component and configured to:

compare a previously determined level width to a target level width, wherein a level width is a width of a threshold voltage distribution corresponding to a state to which the group of memory cells are programmed;

adjust one or more program step characteristics by a respective determined amount to adjust the previously determined level width toward the target level width;

wherein the level width is a sum of level widths among threshold voltage distributions of the plurality of memory cells.

16. The system of claim 15 , wherein the one or more programs step characteristics comprises a step size and a program step duration time, and the respective determined amount is based on a determined relationship between the step size and the program step duration.

17. The system of claim 15 , wherein the processing device is further configured to repeatedly adjust the one or more program step characteristics to maintain a constant level width at a target level width.

18. The system of claim 15 , wherein processing device is further configured to adjust the one or more program step characteristics in response to a change in programming of the memory component.

19. The system of claim 18 , wherein the change in programming comprises a change due to wear cycling of the memory component.

20. The system of claim 18 , wherein the change in programming comprises a temperature change in the memory component.