IP Library Granted Patent US 10,468,386
Granted Patent B1
US 10,468,386 · App. 16/183,961 · Granted Nov 5, 2019

TSV redundancy and TSV test select scheme

Inventors: Homare Sato (Sagamihara, JP); Chikara Kondo (Hachioji, JP); Akira Ide (Sagamihara, JP)
Assignee: Micron Technology, Inc.
H01L25/0657G01R31/2853H01L2225/06541H01L2225/06596
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,468,386
App. No.
16/183,961
Granted
Nov 5, 2019
Kind
B1
Abstract

An apparatus including through substrate vias (TSVs) used to interconnect stacked chips is described. The apparatus according to an embodiment includes a plurality of first selection lines each extending in a first direction; a plurality of second selection lines each extending in a second direction to cross the plurality of first selection lines; and a plurality of a TSV units disposed in intersections of the plurality of first selection lines and the plurality of second selection lines, respectively. Each TSV unit of the plurality of TSV units includes a TSV; a switch coupled to the TSV; and a selection circuit. The selection circuit is configured to control a switching state of the switch responsive to each of an associated one of the plurality of first selection lines and an associated one of the plurality of second selection lines being set to an active level.

Claims (59)

1. An apparatus comprising:

a plurality of first selection lines each extending in a first direction;

a plurality of second selection lines each extending in a second direction to cross the plurality of first selection lines; and

a plurality of a through-substrate via (TSV) units disposed in intersections of the plurality of first selection lines and the plurality of second selection lines, respectively;

wherein each TSV unit of the plurality of TSV units comprises:

a TSV;

a switch coupled to the TSV; and

a selection circuit coupled to an associated one of the plurality of first selection lines and an associated one of the plurality of second selection lines, the selection circuit configured to control a switching state of the switch responsive to each of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to an active level.

2. The apparatus of claim 1 ,

wherein the switch is inserted between the TSV and a voltage line; and

wherein the selection circuit is further configured to cause the switch to form a conductive path between the TSV and the voltage line responsive to each of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to the active level.

3. The apparatus of claim 1 ,

wherein the switch includes a first node coupled to the TSV, a second node coupled to an adjacent TSV unit, and a third node coupled to a signal line; and

wherein the selection circuit is further configured to cause the switch to form a first conductive path between the TSV and the signal line responsive to at least one of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to an inactive level, the selection circuit further configured to cause the switch to form a second conductive path between the adjacent TSV unit and the signal line responsive to each of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to the active level.

4. The apparatus of claim 1 ,

wherein the apparatus further comprises:

a plurality of third selection lines each extending in the first direction; and

a plurality of fourth selection lines each extending in the second direction;

wherein each TSV unit of the plurality of TSV units further comprises an additional switch coupled to the TSV; and

wherein the selection circuit is further coupled to an associated one of the plurality of third selection lines and an associated one of the plurality of fourth selection lines, the selection circuit further configured to control a switching state of the additional switch responsive to each of the associated one of the plurality of third selection lines and the associated one of the plurality of fourth selection lines being set to an active level.

5. The apparatus of claim 1 , wherein the switch coupled to the TSV is configured to be deactivated responsive to the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to an inactive level.

6. The apparatus of claim 1 , wherein each TSV unit of the plurality of TSV units further comprises an additional switch coupled to the TSV.

7. The apparatus of claim 1 , wherein the switch is coupled to a signal line, and

wherein the selection circuit is further configured to control the switch to form a conductive path between the signal line and the TSV responsive to at least one of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to an inactive level.

8. The apparatus of claim 7 , wherein responsive to the at least one of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines set to an inactive level, the selection circuit controls the switch to be deactivated, and the conductive path between the signal line and the TSV is formed by the deactivated switch.

9. The apparatus of claim 1 , wherein the selection circuit further configured to control the switching state of the switch to form a conductive path with another TSV adjacent to the TSV, responsive to each of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines being set to the active level.

10. The apparatus of claim 9 , further comprising a plurality of signal lines coupled to the plurality of TSV units, respectively,

wherein the activated switch forms the conductive path between the signal line and the other TSV adjacent to the TSV.

11. An apparatus comprising:

a plurality of first selection lines extending in a first direction;

a plurality of second selection lines extending in a second direction;

a plurality of selection circuits coupled at respective intersections of the plurality of first selection lines and the plurality of second selection lines; and

a plurality of through-substrate vias (TSVs) coupled to the plurality of selection circuits, respectively,

wherein the plurality of selection circuits are coupled to a plurality of switches, respectively, and each of the selection circuits is configured to control an associated one of the plurality of switches responsive to a logic level of an associated one of the plurality of first selection lines and a logic level of an associated one of the plurality of second selection lines.

12. The apparatus of claim 11 , wherein each switch of the plurality of switches is coupled to a signal line, and

wherein at least one selection circuit of the plurality of selection circuits is further configured to cause at least one associated switch of the plurality of switches to form a first conductive path between at least one associated TSV of the plurality of TSVs and at least one associated signal line of the plurality of signal lines responsive to at least one associated first selection line of the plurality of first selection lines and at least one associated second selection line of the plurality of second selection lines being set to an inactive level.

13. The apparatus of claim 12 , wherein at least one other selection circuit of the plurality of selection circuits is further configured to cause at least one associated switch of the plurality of switches to form a second conductive path between a TSV adjacent to at least one associated TSV of the plurality of TSVs and at least one associated signal line of the plurality of signal lines responsive to each of at least one associated first selection line of the plurality of first selection lines and at least one associated second selection line of the plurality of second selection lines being set to an active level.

14. The apparatus of claim 11 , wherein at least one TSV of the plurality of TSVs is coupled to a voltage line through the associated one of the plurality of switches responsive to an activation of the associated one of the plurality of switches.

15. The apparatus of claim 14 , wherein at least one TSV of the plurality of TSVs is coupled to a voltage line responsive to an active level of each of the associated one of the plurality of first selection lines and the associated one of the plurality of second selection lines.

16. The apparatus of claim 11 , wherein the plurality of TSVs are further coupled to a plurality of additional switches, respectively.

17. An apparatus comprising:

a signal line;

a plurality of through-substrate vias (TSVs);

a plurality of a through-substrate via (TSV) units;

wherein each TSV unit of the plurality of TSV units is associated with a respective TSV of the TSVs of the plurality of TSVs, and each TSV unit comprises:

a switch coupled to the respective TSV and coupled to another signal line;

a register coupled to the signal line and configured to store respective control information provided to the register on the signal line, the register further coupled to the switch,

wherein the register is configured to control a switching state of the switch responsive to control information stored in the register and to control the switch to be deactivated responsive the control information stored in the register being set to an inactive level, and

wherein, the register is further configured to control the switch to form a first conductive path between the TSV and the another signal line responsive to the control information being set to the inactive level.

18. An apparatus comprising:

a signal line;

a plurality of through-substrate vias (TSVs);

a plurality of a through-substrate via (TSV) units;

wherein each TSV unit of the plurality of TSV units is associated with a respective TSV of the TSVs of the plurality of TSVs, and each TSV unit comprises:

a switch coupled to the respective TSV and coupled to another signal line;

a register coupled to the signal line and configured to store respective control information provided to the register on the signal line, the register further coupled to the switch,

wherein the register is configured to control a switching state of the switch responsive to control information stored in the register and to control the switch to be activated responsive the control information stored in the register being set to an active level, and

wherein, the register is further configured to controls the switch to not form a first conductive path between the TSV and the another signal line responsive to the control information being set to the active level.

19. The apparatus of claim 18 , wherein, when the switch is controlled to be activated, the switch is configured to form a second conductive path between the another signal line and an adjacent TSV unit of the plurality of TSV units.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2018
From: SATO, HOMARE; KONDO, CHIKARA; IDE, AKIRA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047450/0008 →
Cited By (1)
US 12,456,536