Management of test resources to perform reliability testing of memory components

1. A method comprising:

determining, by a processing device, filter information associated with a test to be performed on one or more memory components, wherein the filter information comprises at least one of characteristics information or usage information associated with at least a portion of the one or more memory components;

selecting a first test component comprising a first set of memory components of the one or more memory components and a second test component comprising a second set of memory components of the one or more memory components in view of the filter information;

generating test execution information defining a set of test processes of the test;

distributing a first portion of the test execution information corresponding to a first test process to the first test component comprising the first set of memory components;

distributing a second portion of the test execution information corresponding to a second test process to the second test component comprising the second set of memory components, wherein the second test is different from the first test;

receiving, via a first connection with the first test process of the set of test processes, first feedback information; and

determining, based on the first feedback information, a failure of the first test process.

2. The method of claim 1 , further comprising:

receiving, via a second connection with the second test process of the set of test processes, second feedback information; and

determining, based on the second feedback information, a successful execution of the second test.

3. The method of claim 1 , further comprising replicating, using the first feedback information, the first test process on a replication test component.

4. The method of claim 3 , further comprising determining the failure represents an error associated with a memory component of the first set of memory components in view of the replicating of the first test process generating the failure.

5. The method of claim 3 , further comprising determining the failure represents an anomaly associated with a memory component of the first set of memory components in view of the replicating of the first test process generating a successful result.

6. The method of claim 1 , further comprising providing unique connection information to the first test process to establish the first connection to transmit the first feedback information.

7. A system comprising:

a set of memory components; and

a processing device, operatively coupled with the set of memory components, to:

receive a request to perform a test of the set of memory components;

determine filter information corresponding to one or more conditions of the test;

reserve a first test component comprising a first portion of the set of memory components comprising at least one of first characteristics information or first usage information matching the filter information;

reserve a second test component comprising a second portion of the set of memory components comprising at least one of second characteristics information or second usage information matching the filter information;

perform a first sequence of operations of the test using the first portion of the set of memory components;

perform a second sequence of operations of the test using the second portion of the set of memory components, wherein the first sequence is different than the second sequence;

receive, via a connection with a first test process of the test, feedback information indicating a first failed test result; and

replicate the first test process on a replication test component using the feedback information.

8. The system of claim 7 , wherein the first test component is located at a first location and a second test component is located at a second location.

9. The system of claim 7 , wherein the first test component comprises an available test socket comprising the first portion of the set of memory components to be tested.

10. The system of claim 7 , the processing device is further to:

generate test execution information defining the first sequence of operations and the second sequence of operations of the test.

11. The system of claim 10 , the processing device is further to:

receive additional feedback information indicating successful execution of the second sequence of operations.

12. The system of claim 11 , wherein the first portion of the test execution information comprises connection information assigned to the first test process.

13. The system of claim 12 , the processing device is further to:

determine the first failed result represents an error associated with a memory component of the first portion of the set of memory components in view of the first test process replicated on the replication component generating a second failed test result.

14. The system of claim 13 , the processing device is further to:

determine the first failed result represents an anomaly associated with a memory component of the first portion of the set of memory in view of the first test process replicated on the replication component generating a successful test result.

15. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

determining filter information associated with a test to be performed on one or more memory components, wherein the filter information comprises at least one of characteristics information or usage information associated with at least a portion of the one or more memory components;

selecting a first test component comprising a first set of memory components of the one or more memory components and a second test component comprising a second set of memory components of the one or more memory components in view of the filter information;

distributing a first portion of test execution information corresponding to a first test process to the first test component comprising the first set of memory components;

distributing a second portion of the test execution information corresponding to a second test process to the second test component comprising the second set of memory components, wherein the second test is different from the first test;

receiving, via a first connection with the first test process of the set of test processes, first feedback information;

determining, based on the first feedback information, a first failed test result of the first test process; and

replicating, using the first feedback information, the first test process on a first replication test component.

16. The non-transitory computer readable medium of claim 15 , wherein replicating the first test process on the first replication test component generates a second failed test result.

17. The non-transitory computer readable medium of claim 16 , the operations further comprising:

determining the first failed result represents an error associated with a memory component of the first set of memory components in view of the second failed test result.

18. The non-transitory computer readable medium of claim 15 , wherein replicating the first test process on the first replication test component generates a successful test result.

19. The non-transitory computer readable medium of claim 18 , the operations further comprising:

determining the first failed result represents an anomaly associated with a memory component of the set of memory components in view of the successful test result.

20. The non-transitory computer readable medium of claim 15 , wherein each test process of the set of test processes is assigned a unique IP address to use in establishing a connection to provide feedback information associated with a respective test process.