Universal pointers for data exchange in a computer system having independent processors

1. A method, comprising:

executing, in a first processor of a computing system, first instructions, the first instructions configured to use a pointer identifying a virtual memory address used in the first processor;

communicating the pointer from the first processor to a second processor of the computing system during execution of the first instructions, wherein the second processor is separate and independent from the first processor, and the first processor and the second processor have different instruction set architecture (ISA);

communicating with an object name server of the computing system to configure an address translation structure of a memory management unit of the second processor to translate virtual addresses having an identifier of an object to physical addresses; and

executing second instructions in the second processor, the second instructions configured to access the virtual memory address using the pointer received from the first processor;

wherein the virtual memory address has a predetermined number of bits, including a first predetermined number of bits representing the identifier of the object and a second predetermined number of bits representing a memory location offset within the object;

wherein the first instructions executed in the first processor constructs the pointer to identify a memory location in the computing system; and the second processor uses the virtual memory address to access the memory location in the computing system; and

wherein the memory location is coupled to and accessible to the second processor while the memory location is accessible to the first processor via communication with the second processor.

2. The method of claim 1 , wherein the pointer is communicated from the first processor to a second processor via a computer network.

3. The method of claim 1 , wherein the memory location is in a memory of the second processor or a storage device in the computing system.

4. The method of claim 1 , further comprising:

converting, by the memory management unit of the second processor, the virtual memory address into a physical memory address; and

accessing, by the memory management unit, the physical memory address.

5. The method of claim 4 , further comprising:

loading an instruction from the physical memory address into the second processor; and

executing the instruction in the second processor.

6. The method of claim 4 , further comprising:

loading an operand from the physical memory address into the second processor in response to the virtual memory address being in a register in the second processor; and

executing an instruction on the operand in the second processor.

7. The method of claim 6 , further comprising:

storing, by the first processor, a computing result at the physical memory address using the virtual memory address during the execution of the first instructions, wherein the computing result is the operand in the executing the instruction in the second processor.

8. The method of claim 4 , wherein the virtual memory address has 128 bits; and

the memory location offset has 64 bits.

9. The method of claim 1 , wherein the first processor is running a first operating system and the second processor is running a second operating system different from the first operating system.

10. The method of claim 9 , wherein the first operating system is Linux and the second operating system is Windows.

11. The method of claim 9 , wherein the first operating system is Windows and the second operating system is Linux.

12. A non-transitory computer storage medium storing first instructions which, when executed in a first processor of a computing system, cause the first processor to perform a method, the method comprising:

executing, in the first processor of the computing system, the first instructions;

constructing, by the first processor, a pointer identifying a virtual memory address accessible by the first processor;

communicating the pointer from the first processor to a second processor of the computing system during execution of the first instructions; and

communicating with an object name server of the computing system to configure an address translation structure of a memory management unit of the second processor to translate virtual addresses having an identifier of an object to physical addresses;

wherein the second processor is separate and independent from the first processor and the first processor and the second processor have different instruction set architecture (ISA);

wherein during execution of second instructions in the second processor, the second processor accesses the virtual memory address according to the pointer received from the first processor;

wherein the virtual memory address has a predetermined number of bits, including a first predetermined number of bits representing the identifier of the object and a second predetermined number of bits representing a memory location offset within the object;

wherein the first instructions executed in the first processor constructs the pointer to identify a memory location in the computing system; and the second processor uses the virtual memory address to access the memory location in the computing system using the pointer; and

wherein the memory location is coupled to and accessible to the second processor while the memory location is accessible to the first processor via communication with the second processor.

13. The non-transitory computer storage medium of claim 12 , wherein the pointer is communicated from the first processor to a second processor via a computer network.

14. The non-transitory computer storage medium of claim 13 , wherein the virtual memory address has 128 bits, including the identifier of the object and a 64-bit memory location offset relative to the object.

15. A non-transitory computer storage medium storing instructions which, when executed in a computing system having a first processor and a second processor that is separate and independent from the first processor and the first processor and the second processor have different instruction set architecture (ISA), cause the computing system to perform a method, the method comprising:

receiving, in the second processor, a pointer from the first processor, wherein during execution of first instructions in the first processor, the first processor generates the pointer identifying a virtual memory address accessible by the first processor;

communicating, by a memory management unit of the second processor, with an object name server of the computing system to configure an address translation structure of the memory management unit to translate virtual addresses having an identifier of an object to physical addresses;

executing, in the second processor, second instructions; and

accessing, by the second processor in accordance with the pointer, the virtual memory address during execution of the second instructions in the second processor, wherein the virtual memory address has a predetermined number of bits, including a first predetermined number of bits representing the identifier of the object and a second predetermined number of bits representing a memory location offset within the object;

wherein the first instructions executed in the first processor constructs the pointer to identify a memory location in the computing system; and the second processor uses the virtual memory address to access the memory location in the computing system using the pointer; and

wherein the memory location is coupled to and accessible to the second processor while the memory location is accessible to the first processor via communication with the second processor.

16. The non-transitory computer storage medium of claim 15 , the method further comprising:

converting, by the memory management unit of the second processor, the virtual memory address into a physical memory address; and

accessing, by the memory management unit, the physical memory address.

17. The non-transitory computer storage medium of claim 16 , wherein the accessing of the physical memory address includes loading, from the physical memory address, an instruction of the object or an operand of an instruction operating on the object.

18. The non-transitory computer storage medium of claim 16 , the method further comprising:

communicating, by the memory management unit of the second processor, with the object name server of the computing system to retrieve the memory location of the object in the computing system; and

configuring the address translation structure of the memory management unit using the memory location retrieved from the object name server, wherein the converting of the virtual memory address into the physical memory address is performed using the address translation structure configured using the memory location.