Error detection code hold pattern synchronization
View Patent ↗A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.
1. A method, comprising:
detecting a first scenario, comprising an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both;
upon detection of the first scenario:
asserting an error detection code (EDC) hold reset; and
de-asserting the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to a data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
2. The method of claim 1 , comprising:
detecting an occurrence of the falling edge of the EDC hold reset;
triggering the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.
3. The method of claim 1 , wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.
4. The method of claim 1 , wherein the memory device comprises dynamic random-access memory (DRAM).
5. The method of claim 1 , comprising:
transmitting the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.
6. The method of claim 1 , wherein the WCK_t frequency is twice the CK_t frequency.
7. The method of claim 1 , comprising asserting the error detection code (EDC) hold reset, via EDC hold pattern generation circuitry, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.
8. An electronic device, comprising:
a command clock (CK_t clock);
a data path clock (WCK_t);
error detection code (EDC) hold pattern generation circuitry, configured to:
upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
assert an EDC hold reset; and
de-assert the EDC hold reset synchronous to a rising edge of the command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
9. The electronic device of claim 8 , comprising:
detecting an occurrence of the falling edge of the EDC hold reset;
triggering the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.
10. The electronic device of claim 8 , comprising the memory device, wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.
11. The electronic device of claim 8 , comprising the memory device, wherein the memory device comprises dynamic random-access memory (DRAM).
12. The electronic device of claim 8 , comprising the memory device, wherein the electronic device is configured to transmit the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.
13. The electronic device of claim 8 , wherein the WCK_t frequency is twice the CK_t frequency.
14. The electronic device of claim 8 , wherein the EDC hold pattern generation circuitry is configured to assert the error detection code (EDC) hold reset, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.
15. An error detection code (EDC) hold pattern generation circuitry, configured to:
upon detection of an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both:
assert an EDC hold reset; and
de-assert the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to the data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.
16. The EDC hold pattern generation circuitry of claim 15 , configured to:
detect an occurrence of the falling edge of the EDC hold reset;
trigger the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.
17. The EDC hold pattern generation circuitry of claim 15 , wherein the memory device comprises: double data rate type three synchronous random-access (DDR3) memory, double data rate type four synchronous random-access (DDR4) memory, double data rate type five synchronous random-access (DDR5) memory, double data rate type five synchronous graphics random-access (GDDR5) memory, double data rate type five x synchronous graphics random-access (GDDR5x) memory, double data rate type six synchronous graphics random-access (GDDR6) memory, or any combination thereof.
18. The EDC hold pattern generation circuitry of claim 15 , wherein the memory device comprises dynamic random-access memory (DRAM).
19. The EDC hold pattern generation circuitry of claim 15 , configured to transmit the EDC hold pattern and error correction checksum data via common EDC pads of the memory device.
20. The EDC hold pattern generation circuitry of claim 15 , configured to assert the error detection code (EDC) hold reset, by timing a first data flip flop of EDC hold pattern synchronization logic to the CK_t clock and providing, via the first data flip flop, the EDC hold reset to the EDC hold pattern generation circuitry.