Methods of forming conductive vias and methods of forming memory circuitry

1. A method of forming conductive vias of integrated circuitry, comprising:

forming first openings in a first masking material, the first openings being spaced along a line passing across the first openings;

lining sidewalls of the first openings with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring;

removing the first masking material along the line to form a void space between immediately-adjacent of the rings;

forming a mask comprising the rings and a third opening in third masking material, the third opening extending along the line above and across multiple of the rings and multiple of the second openings;

using the mask as an etch mask while etching into substrate material that is exposed through the third opening to form contact openings in the substrate material that are spaced along the line; and

forming conductive material in the contact openings to form conductive vias.

2. The method of claim 1 wherein the line is straight.

3. The method of claim 1 wherein the line is not straight.

4. The method of claim 1 wherein the rings are individually longer than they are wide.

5. The method of claim 1 wherein the conductive vias at least partially overlap one another in a straight-line horizontal cross-section.

6. The method of claim 5 wherein the conductive vias are of the same size and shape area relative one another in the straight-line horizontal cross-section, the conductive-via areas totally overlapping relative one another in the straight-line horizontal cross-section.

7. The method of claim 1 wherein the first and second masking materials are of different compositions relative one another, the removing of the first masking material being selective relative to the second masking material.

8. The method of claim 1 wherein the forming of the first openings in the first masking material comprises:

forming narrower first openings in the first masking material;

laterally etching the first material to transform the narrower first openings into wider first openings; and

the rings being individually formed in the wider first openings.

9. The method of claim 1 wherein the removing of the first masking material occurs before forming the mask.

10. The method of claim 1 wherein the removing of the first masking material occurs through the third opening after forming the mask.

11. The method of claim 1 wherein the third opening is centered relative to centers of the multiple second openings.

12. The method of claim 1 wherein the third opening exposes less-than-all of individual of said multiple rings and less-than-all of individual of said second openings.

13. The method of claim 1 wherein the third masking material comprises an outermost material of the same composition as that of the first masking material.

14. The method of claim 13 wherein the first and second masking materials are of different compositions relative one another, the removing of the first masking material being selective relative to the second masking material.

15. The method of claim 1 wherein said using comprises forming the contact openings in the substrate material to be self-aligned along the line.

16. The method of claim 1 wherein the substrate material comprises outer hard-masking material and further comprising:

using the rings as an etching mask while etching into the hard-masking material to form rings in the hard-masking material; and

said using comprising using the etch mask to form the contact openings in the substrate material to be self-aligned along the line.

17. The method of claim 16 wherein the substrate material comprises an antireflective coating above the hard-masking material.

18. The method of claim 17 comprising elemental silicon between the hard-masking material and the antireflective coating.

19. The method of claim 16 wherein the hard-masking material comprises carbon above elemental silicon.

20. A method of forming conductive vias of integrated circuitry, comprising:

forming first openings in a first masking material, the first openings being spaced along a straight line passing across the first openings;

lining sidewalls of the first openings with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring, the ring being longer than it is wide, the first and second masking materials being of different compositions relative one another;

removing the first masking material selectively relative to the second masking material along the straight line to form a void space between immediately-adjacent of the rings;

after removing the first masking material, forming a mask comprising the rings and a third opening in third masking material; the third openings extending along the straight line above and across multiple of the rings, multiple of the second openings, and multiple of the void spaces; the third opening being centered relative to centers of the multiple second openings;

the third opening exposing less-than-all of individual of said multiple rings and less-than-all of individual of said second openings;

using the mask as an etch mask while etching into substrate material that is exposed through the third opening to form contact openings in the substrate material that are spaced along the straight line, said using comprises forming the contact openings in the substrate material to be self-aligned along the straight line; and

forming conductive material in the contact openings to form conductive vias, the conductive-vias at least partially overlapping relative one another in the straight-line horizontal cross-section.

21. The method of claim 20 wherein the forming of the first openings in the first masking material comprises:

forming narrower first openings in the first masking material;

laterally etching the first material to transform the narrower first openings into wider first openings; and

the rings being individually formed in the wider first openings.

22. The method of claim 20 wherein the substrate material comprises outer hard-masking material and further comprising:

using the rings as an etching mask while etching into the hard-masking material to form rings in the hard-masking material; and

said using comprising using the etch mask to form the contact openings in the substrate material to be self-aligned along the line.

23. A method of forming conductive vias, comprising:

forming a plurality of conductive lines extending longitudinally from a first substrate area into a second substrate area;

forming first openings in a first masking material, the first openings being spaced along a line passing across the first openings, the line of the first openings crossing the conductive lines in the second substrate area;

lining sidewalls of the first openings with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring, individual of the second openings being directly above a single individual of the conductive lines in the second substrate area;

removing the first masking material along the line of the first openings to form a void space between immediately-adjacent of the rings, individual of the void spaces being directly above another single individual of the conductive lines in the second substrate area;

forming a mask comprising the rings and a third opening in third masking material, the third opening extending above and across multiple of the rings and multiple of the second openings;

using the mask as an etch mask while etching into substrate material that is exposed through the third opening to form spaced contact openings in the substrate material to the individual conductive lines; and

forming conductive material in the contact openings to form conductive vias in the second substrate area that are individually directly electrically coupled to one of the individual conductive lines.

24. The method of claim 23 wherein the individual first openings are longitudinally elongated, and the rings are individually longer than they are wide.

25. The method of claim 23 wherein the individual first openings are longitudinally elongated parallel the conductive lines and the rings are individually longitudinally elongated parallel the conductive lines.

26. The method of claim 23 wherein the line of the first openings is straight.

27. A method of forming memory circuitry, comprising:

forming a plurality of conductive lines extending longitudinally from a memory array area to a peripheral circuitry area adjacent the memory array area, the conductive lines comprising a series of (a) wordlines, or (b) digitlines;

forming first openings in a first masking material in the peripheral circuitry area, the first openings being spaced along a line passing across the first openings, the line of the first openings crossing the conductive lines in the peripheral circuitry area;

lining sidewalls of the first openings with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring, individual of the second openings being directly above a single individual of the conductive lines in the peripheral circuitry area;

removing the first masking material along the line of the first openings to form a void space between immediately-adjacent of the rings, individual of the void spaces being directly above another single individual of the conductive lines in the peripheral circuitry area;

forming a mask comprising the rings and a third opening in third masking material, the third opening extending across multiple of the rings and multiple of the second openings;

using the mask as an etch mask while etching into substrate material that is exposed through the third opening to form spaced peripheral contact openings in the substrate material to the individual conductive lines;

forming conductive material in the contact openings to form conductive vias in the peripheral circuitry area that are individually directly electrically coupled to one of the individual conductive lines.

28. The method of claim 27 wherein the series is (a).

29. The method of claim 27 wherein the series is (b).